Issued Patents All Time
Showing 126–150 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10714181 | Memory cell | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Chien-Chen Lin | 2020-07-14 |
| 10685704 | Static random access memory circuit | Wei-Cheng Wu, Wei Min Chan, Hung-Jen Liao, Ping-Wei Wang | 2020-06-16 |
| 10672776 | Memory circuit having resistive device coupled with supply voltage line | Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2020-06-02 |
| 10650882 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin | 2020-05-12 |
| 10651114 | Apparatus and method of three dimensional conductive lines | Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang | 2020-05-12 |
| 10636458 | Sense amplifier layout for FinFET technology | Chien-Chi TIEN, Kao-Cheng Lin, Jung-Hsuan Chen | 2020-04-28 |
| 10559333 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2020-02-11 |
| 10541007 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2020-01-21 |
| 10535658 | Memory device with reduced-resistance interconnect | Sahil Preet Singh | 2020-01-14 |
| 10529415 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Hung-Jen Liao | 2020-01-07 |
| 10510403 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Sahil Preet Singh | 2019-12-17 |
| 10510739 | Method of providing layout design of SRAM cell | Hidehiro Fujiwara, Tetsu Ohtou, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno | 2019-12-17 |
| 10503421 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2019-12-10 |
| 10490267 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Sahil Preet Singh, Jung-Hsuan Chen, Avinash Chander, Albert Ying | 2019-11-26 |
| 10431295 | Static random access memory and method of controlling the same | Li-Wen Wang, Chih-Yu Lin, Hung-Jen Liao | 2019-10-01 |
| 10411019 | SRAM cell word line structure with reduced RC effects | Hidehiro Fujiwara, Wei Min Chan, Chih-Yu Lin, Hung-Jen Liao | 2019-09-10 |
| 10373964 | Method of writing to memory circuit using resistive device | Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2019-08-06 |
| 10354952 | Memory cell having multi-level word line | Hidehiro Fujiwara, Li-Wen Wang, Hung-Jen Liao | 2019-07-16 |
| 10332896 | SRAM circuits with aligned gate electrodes | Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu | 2019-06-25 |
| 10319421 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2019-06-11 |
| 10319435 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Hung-Jen Liao | 2019-06-11 |
| 10276231 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Mahmut Sinangil | 2019-04-30 |
| 10275561 | Method for eliminating false paths of a circuit unit to be implemented using a system | Chun-Jiun Dai, Hung-Jen Liao, Wei Min Chan | 2019-04-30 |
| 10276579 | Layout design for manufacturing a memory cell | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan | 2019-04-30 |
| 10268787 | Hybrid timing analysis method and associated system and non-transitory computer readable medium | Chun-Jiun Dai, Wei Min Chan, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2019-04-23 |