Issued Patents All Time
Showing 176–200 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837130 | Digtial circuit structures to control leakage current | Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Hung-Jen Liao | 2017-12-05 |
| 9824729 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2017-11-21 |
| 9812191 | Memory circuit with negative voltage assist | Avinash Chander | 2017-11-07 |
| 9799394 | Static random access memory (SRAM) with recovery circuit for a write operation | Wei-Cheng Wu, Kao-Cheng Lin, Wei Min Chan | 2017-10-24 |
| 9762216 | Level shifter circuit using boosting circuit | Mahmut Sinangil, Hsin-Hsin Ko, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2017-09-12 |
| 9741429 | Memory with write assist circuit | Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2017-08-22 |
| 9704565 | Method of using a static random access memory | Wei-Cheng Wu, Wei Min Chan, Hung-Jen Liao, Ping-Wei Wang | 2017-07-11 |
| 9685223 | Voltage controller | Wei-Cheng Wu, Wei Min Chan, Hung-Jen Liao | 2017-06-20 |
| 9659620 | Memory device with self-boosted mechanism | Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2017-05-23 |
| 9640251 | Multi-port memory cell | Hidehiro Fujiwara, Kao-Cheng Lin, Hung-Jen Liao | 2017-05-02 |
| 9607683 | Emulator for imulating an operation of a SRAM | Hidehiro Fujiwara, Hung-Jen Liao | 2017-03-28 |
| 9601162 | Memory devices with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2017-03-21 |
| 9583438 | Interconnect structure with misaligned metal lines coupled using different interconnect layer | Jhon Jhy Liaw | 2017-02-28 |
| 9576645 | Three dimensional dual-port bit cell and method of using same | Wei Min Chan, Wei-Cheng Wu | 2017-02-21 |
| 9552873 | Memory device | Tzu-Kuei Lin, Hung-Jen Liao | 2017-01-24 |
| 9536598 | Memory arrangement | Wei-Cheng Wu, Hung-Jen Liao | 2017-01-03 |
| 9524920 | Apparatus and method of three dimensional conductive lines | Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang | 2016-12-20 |
| 9496026 | Memory device with stable writing and/or reading operation | Mohammed Hasan Taufique, Hidehiro Fujiwara, Hung-Jen Liao | 2016-11-15 |
| 9466493 | Sense amplifier layout for FinFET technology | Chien-Chi TIEN, Kao-Cheng Lin, Jung-Hsuan Chen | 2016-10-11 |
| 9449661 | Memory device | Li-Wen Wang, Chih-Yu Lin | 2016-09-20 |
| 9449667 | Memory circuit having shared word line | Hidehiro Fujiwara, Li-Wen Wang, Hung-Jen Liao | 2016-09-20 |
| 9425095 | Distributed metal routing | You-Cheng Xiao, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao | 2016-08-23 |
| 9418729 | Multi-port memory cell | Hidehiro Fujiwara, Kao-Cheng Lin, Hung-Jen Liao | 2016-08-16 |
| 9412742 | Layout design for manufacturing a memory cell | Hidehiro Fujiwara, Kao-Cheng Lin, Ming-Yi Lee, Hung-Jen Liao | 2016-08-09 |
| 9343140 | Boosted read write word line | Chih-Yu Lin, Li-Wen Wang, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2016-05-17 |