Issued Patents All Time
Showing 151–175 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10204660 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2019-02-12 |
| 10176864 | Static random access memory circuits | Wei-Cheng Wu, Wei Min Chan, Hung-Jen Liao, Ping-Wei Wang | 2019-01-08 |
| 10163491 | Memory circuit having shared word line | Hidehiro Fujiwara, Li-Wen Wang, Hung-Jen Liao | 2018-12-25 |
| 10163497 | Three dimensional dual-port bit cell and method of using same | Wei Min Chan, Wei-Cheng Wu | 2018-12-25 |
| 10163759 | Apparatus and method of three dimensional conductive lines | Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang | 2018-12-25 |
| 10157666 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Sahil Preet Singh, Jung-Hsuan Chen, Avinash Chander, Albert Ying | 2018-12-18 |
| 10153035 | SRAM-based authentication circuit | Chien-Chen Lin, Wei Min Chan, Chih-Yu Lin, Shih-Lien Linus Lu | 2018-12-11 |
| 10153038 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Sahil Preet Singh | 2018-12-11 |
| 10134737 | Memory device with reduced-resistance interconnect | Sahil Preet Singh | 2018-11-20 |
| 10083739 | Three-dimensional three-port bit cell and method of assembling same | Tzu-Kuei Lin, Hung-Jen Liao, Ching-Wei Wu | 2018-09-25 |
| 10062419 | Digtial circuit structures | Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Hung-Jen Liao | 2018-08-28 |
| 10037796 | Generating a collapsed VDD using a write-assist column to decrease a write voltage | Sahil Preet Singh | 2018-07-31 |
| 10032490 | Sense amplifier layout for FinFET technology | Chien-Chi TIEN, Kao-Cheng Lin, Jung-Hsuan Chen | 2018-07-24 |
| 9997436 | Apparatus and method of three dimensional conductive lines | Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang | 2018-06-12 |
| 9997235 | Semiconductor memory with respective power voltages for plurality of memory cells | Wei-Cheng Wu, Chih-Yu Lin, Kao-Cheng Lin, Wei Min Chan | 2018-06-12 |
| 9997219 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2018-06-12 |
| 9928899 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Sahil Preet Singh, Jung-Hsuan Chen, Avinash Chander, Albert Ying | 2018-03-27 |
| 9922700 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Sahil Preet Singh | 2018-03-20 |
| 9905292 | Three dimensional dual-port bit cell and method of using same | Wei Min Chan, Wei-Cheng Wu | 2018-02-27 |
| 9886996 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Mahmut Sinangil | 2018-02-06 |
| 9871046 | SRAM circuits with aligned gate electrodes | Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu | 2018-01-16 |
| 9865605 | Memory circuit having resistive device coupled with supply voltage line | Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2018-01-09 |
| 9865542 | Interconnect structure with misaligned metal lines coupled using different interconnect layer | Jhon Jhy Liaw | 2018-01-09 |
| 9853035 | Layout scheme and method for forming device cells in semiconductor devices | Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao | 2017-12-26 |
| 9842627 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2017-12-12 |