Issued Patents All Time
Showing 226–250 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8723265 | Semiconductor structure with dummy polysilicon lines | Wei Min Chan, Shao-Yu Chou, Hung-Jen Liao | 2014-05-13 |
| 8713491 | Pre-colored methodology of multiple patterning | Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2014-04-29 |
| 8693265 | Data inversion for dual-port memory | Tzu-Kuei Lin, Jonathan Tsung-Yung Chang, Hung-Jen Liao, Jhon Jhy Liaw | 2014-04-08 |
| 8692333 | Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance | You-Cheng Xiao, Jung-Hsuan Chen, Shao-Yu Chou | 2014-04-08 |
| 8670637 | Optical clock signal distribution using through-silicon vias | Shih-Cheng Chang, Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu | 2014-03-11 |
| 8665658 | Tracking cell and method for semiconductor memories | — | 2014-03-04 |
| 8644087 | Leakage-aware keeper for semiconductor memory | Jihi-Yu Lin, Li-Wen Wang, Wei Min Chan | 2014-02-04 |
| 8610236 | Edge devices layout for improved performance | Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao, Li-Chun Tien | 2013-12-17 |
| 8605535 | Integrated circuits, systems, and methods for reducing leakage currents in a retention mode | Cheng Hung Lee | 2013-12-10 |
| 8601411 | Pre-colored methodology of multiple patterning | Wei Min Chan, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2013-12-03 |
| 8576655 | Semiconductor memories | Wei Min Chan, Jihi-Yu Lin, Hsien-Yu Pan, Hung-Jen Liao | 2013-11-05 |
| 8570823 | Sense amplifier with low sensing margin and high device variation tolerance | Hsien-Yu Pan, Shao-Yu Chou | 2013-10-29 |
| 8559251 | Memory circuit and method of writing datum to memory circuit | Chih-Yu Lin, Wei Min Chan, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2013-10-15 |
| 8477527 | SRAM timing cell apparatus and methods | Li-Wen Wang, Shao-Yu Chou, Jihi-Yu Lin, Wei Min Chan, Ping-Wei Wang | 2013-07-02 |
| 8455354 | Layouts of POLY cut openings overlapping active regions | Jung-Hsuan Chen, Li-Chun Tien, Hung-Jen Liao | 2013-06-04 |
| 8406028 | Word line layout for semiconductor memory | Tzu-Kuei Lin, Hung-Jen Liao, Ping-Wei Wang, Huai-Ying Huang | 2013-03-26 |
| 8391097 | Memory word-line driver having reduced power consumption | Wei Min Chan, Chen-Lin Yang, Hsiu-Hui Yang, Shao-Yu Chou | 2013-03-05 |
| 8363454 | SRAM bit cell | Ping-Wei Wang, Hung-Jen Liao, Jihi-Yu Lin, Shao-Yu Chou | 2013-01-29 |
| 8358165 | Ultra-low voltage level shifting circuit | Shao-Yu Chou, Jui-Jen Wu | 2013-01-22 |
| 8305832 | Integrated circuits, systems, and methods for reducing leakage currents in a retention mode | Cheng Hung Lee | 2012-11-06 |
| 8295116 | Circuit and method of providing current compensation | Shao-Yu Chou | 2012-10-23 |
| 8258848 | Level shifter | — | 2012-09-04 |
| 8144501 | Read/write margin improvement in SRAM design using dual-gate transistors | Jui-Jen Wu | 2012-03-27 |
| 8139436 | Integrated circuits, systems, and methods for reducing leakage currents in a retention mode | Cheng Hung Lee | 2012-03-20 |
| 8111542 | 8T low leakage SRAM cell | Jui-Jen Wu, Shao-Yu Chou, Hung-Jen Liao | 2012-02-07 |