Issued Patents All Time
Showing 26–50 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12068253 | Semiconductor structure with two-dimensional conductive structures | Shu-Wei Li, Yu-Chen Chan, Meng-Pei Lu, Shin-Yi Yang | 2024-08-20 |
| 12062612 | Semiconductor device structure and methods of forming the same | Shu-Wei Li, Guanyu Luo, Shin-Yi Yang | 2024-08-13 |
| 12051683 | Semiconductor packages and methods for forming the same | Han-Tang Hung, Shin-Yi Yang, Shau-Lin Shue | 2024-07-30 |
| 12051645 | Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang | 2024-07-30 |
| 12051643 | Hybrid via interconnect structure | Chin-Lung Chung, Shin-Yi Yang | 2024-07-30 |
| 12027419 | Semiconductor device including liner structure | Ching-Fu Yeh, Yu-Chen Chan, Guanyu Luo, Meng-Pei Lu, Chao-Hsien Peng +2 more | 2024-07-02 |
| 11978663 | Integrated circuit interconnect structure having discontinuous barrier layer and air gap | Chin-Lung Chung, Shin-Yi Yang | 2024-05-07 |
| 11967552 | Methods of forming interconnect structures in semiconductor fabrication | Shau-Lin Shue | 2024-04-23 |
| 11948837 | Semiconductor structure having vertical conductive graphene and method for forming the same | Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang | 2024-04-02 |
| 11929326 | Method of forming graphene barrier layer in interconnect structure | Shin-Yi Yang, Shau-Lin Shue | 2024-03-12 |
| 11908794 | Protection liner on interconnect wire to enlarge processing window for overlying interconnect via | Shin-Yi Yang, Hsin-Yen Huang, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu | 2024-02-20 |
| 11901349 | Semiconductor packages and methods for forming the same | Han-Tang Hung, Shin-Yi Yang, Shau-Lin Shue | 2024-02-13 |
| 11854987 | Semiconductor packages with interconnection features in a seal region and methods for forming the same | Shin-Yi Yang, Shau-Lin Shue | 2023-12-26 |
| 11854944 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Shau-Lin Shue | 2023-12-26 |
| 11848190 | Barrier-less structures | Hsin-Ping Chen, Yung-Hsu Wu, Chia-Tien Wu, Min Cao, Shau-Lin Shue +1 more | 2023-12-19 |
| 11830910 | Semiconductor structure having air gaps and method for manufacturing the same | Chieh-Han Wu, Hwei-Jay CHU, An-Dih Yu, Tzu-Hui Wei, Cheng-Hsiung Tsai +2 more | 2023-11-28 |
| 11810816 | Chemical mechanical polishing topography reset and control on interconnect metal lines | Shih-Kang Fu | 2023-11-07 |
| 11749643 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Shau-Lin Shue | 2023-09-05 |
| 11742239 | Methods of performing chemical-mechanical polishing process in semiconductor devices | Shih-Kang Fu, Shau-Lin Shue | 2023-08-29 |
| 11735513 | Integrated chip having a back-side power rail | Shin-Yi Yang, Shau-Lin Shue | 2023-08-22 |
| 11728264 | Hybrid interconnect structure for self aligned via | Shin-Yi Yang, Shau-Lin Shue | 2023-08-15 |
| 11721627 | Graphene layer for reduced contact resistance | Shin-Yi Yang, Shau-Lin Shue | 2023-08-08 |
| 11715689 | Method of forming metal interconnection | Shin-Yi Yang, Shau-Lin Shue, Tz-Jun Kuo | 2023-08-01 |
| 11710700 | Graphene-assisted low-resistance interconnect structures and methods of formation thereof | Shin-Yi Yang, Yu-Chen Chan, Hai-Ching Chen, Shau-Lin Shue | 2023-07-25 |
| 11682620 | Graded metallic liner for metal interconnect structures and methods for forming the same | Shu-Wei Li, Guanyu Luo, Shin-Yi Yang | 2023-06-20 |