Issued Patents All Time
Showing 51–75 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11682616 | Semiconductor structure and method for forming the same | Meng-Pei Lu, Shin-Yi Yang, Shu-Wei Li, Chin-Lung Chung | 2023-06-20 |
| 11670595 | Semiconductor device structure and methods of forming the same | Yu-Chen Chan, Shu-Wei Li, Shin-Yi Yang, Shau-Lin Shue | 2023-06-06 |
| 11652055 | Interconnect structure with hybrid barrier layer | Shu-Wei Li, Shin-Yi Yang, Shau-Lin Shue | 2023-05-16 |
| 11640940 | Methods of forming interconnection structure including conductive graphene layers | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Shau-Lin Shue | 2023-05-02 |
| 11605558 | Integrated circuit interconnect structure having discontinuous barrier layer and air gap | Chin-Lung Chung, Shin-Yi Yang | 2023-03-14 |
| 11605591 | Semiconductor device structure and methods of forming the same | Shu-Wei Li, Guanyu Luo, Shin-Yi Yang | 2023-03-14 |
| 11594483 | Semiconductor structure | Shin-Yi Yang, Shau-Lin Shue | 2023-02-28 |
| 11551967 | Via structure and methods for forming the same | Meng-Pei Lu, Shin-Yi Yang, Tz-Jun Kuo | 2023-01-10 |
| 11545389 | Titanium-containing diffusion barrier for CMP removal rate enhancement and contamination reduction | Shih-Kang Fu, Shau-Lin Shue | 2023-01-03 |
| 11532547 | Interconnect structures with low-aspect-ratio contact vias | Cheng-Hsiung Tsai, Chung-Ju Lee | 2022-12-20 |
| 11532549 | Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang | 2022-12-20 |
| 11482451 | Interconnect structures | Guanyu Luo, Shin-Yi Yang, Shau-Lin Shue | 2022-10-25 |
| 11462470 | Method of forming graphene and metallic cap and barrier layers for interconnects | Shin-Yi Yang, Shau-Lin Shue | 2022-10-04 |
| 11450602 | Hybrid method for forming semiconductor interconnect structure | Shih-Kang Fu, Shau-Lin Shue | 2022-09-20 |
| 11404366 | Hybrid interconnect structure for self aligned via | Shin-Yi Yang, Shau-Lin Shue | 2022-08-02 |
| 11342219 | Chemical mechanical polishing topography reset and control on interconnect metal lines | Shih-Kang Fu | 2022-05-24 |
| 11322391 | Interconnect structure without barrier layer on bottom surface of via | Tz-Jun Kuo, Chien-Hsin Ho | 2022-05-03 |
| 11309241 | Protection liner on interconnect wire to enlarge processing window for overlying interconnect via | Shin-Yi Yang, Hsin-Yen Huang, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu | 2022-04-19 |
| 11296026 | Semiconductor device and manufacturing method thereof | Shau-Lin Shue | 2022-04-05 |
| 11211256 | Method with CMP for metal ion prevention | Shih-Kang Fu, Shau-Lin Shue | 2021-12-28 |
| 11205618 | Graphene barrier layer | Shin-Yi Yang, Shau-Lin Shue | 2021-12-21 |
| 11201106 | Semiconductor device with conductors embedded in a substrate | Hsin-Ping Chen, Shau-Lin Shue | 2021-12-14 |
| 11152255 | Methods of performing chemical-mechanical polishing process in semiconductor devices | Shih-Kang Fu, Shau-Lin Shue | 2021-10-19 |
| 11127680 | Semiconductor device and manufacturing method thereof | Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Shau-Lin Shue | 2021-09-21 |
| 11114374 | Graphene enabled selective barrier layer formation | Shin-Yi Yang, Guanyu Luo, Chin-Lung Chung, Shau-Lin Shue | 2021-09-07 |