Issued Patents All Time
Showing 26–50 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11916077 | Method for routing local interconnect structure at same level as reference metal line | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang +5 more | 2024-02-27 |
| 11916017 | Signal conducting line arrangements in integrated circuits | Wei Ling Chang, Chih-Liang Chen, Guo-Huei Wu | 2024-02-27 |
| 11894238 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2024-02-06 |
| 11854786 | Deep lines and shallow lines in signal conducting paths | Wei-An Lai, Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2023-12-26 |
| 11848190 | Barrier-less structures | Hsin-Ping Chen, Yung-Hsu Wu, Min Cao, Ming-Han Lee, Shau-Lin Shue +1 more | 2023-12-19 |
| 11842966 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao +2 more | 2023-12-12 |
| 11842967 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin | 2023-12-12 |
| 11817392 | Integrated circuit | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-11-14 |
| 11769695 | Semiconductor structure including low-resistance interconnect and integrated circuit device having the same | Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang +2 more | 2023-09-26 |
| 11764106 | Semiconductor device and method of manufacture | Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Hsin-Ping Chen, Shau-Lin Shue | 2023-09-19 |
| 11729969 | Semiconductor device and method of operating the same | Hsiang-Wei Liu, Wei-Chen Chu | 2023-08-15 |
| 11715636 | Method of manufacturing a semiconductor device | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-08-01 |
| 11682618 | Hybrid metal line structure | Pokuan Ho, Hsin-Ping Chen, Wei-Chen Chu | 2023-06-20 |
| 11640924 | Structure and method for interconnection with self-alignment | Tai-I Yang, Yu-Chieh Liao, Hsin-Ping Chen, Hai-Ching Chen, Shau-Lin Shue | 2023-05-02 |
| 11637064 | Advanced metal connection with metal cut | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang +6 more | 2023-04-25 |
| 11581298 | Zero mask high density capacitor | Chung-Hui Chen, Wan-Te Chen, Cheng-Hsiang Hsieh | 2023-02-14 |
| 11488861 | Method for manufacturing an interconnect structure having a selectively formed bottom via | Po-Kuan HO | 2022-11-01 |
| 11482473 | Semiconductor device, and associated method and system | Shih-Wei Peng, Jiann-Tyng Tzeng | 2022-10-25 |
| 11387113 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2022-07-12 |
| 11264277 | Semiconductor device with spacers for self aligned vias | Pokuan Ho, Hsin-Ping Chen | 2022-03-01 |
| 11257673 | Dual spacer metal patterning | Yu-Chieh Liao, Cheng-Chi Chuang, Tai-I Yang, Hsin-Ping Chen | 2022-02-22 |
| 11257670 | Method of manufacturing a semiconductor device, and associated semiconductor device and system | Shih-Wei Peng, Jiann-Tyng Tzeng | 2022-02-22 |
| 11158580 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin | 2021-10-26 |
| 11107725 | Interconnect structure and manufacturing method for the same | Hsiang-Wei Liu, Wei-Chen Chu, Tai-I Yang | 2021-08-31 |
| 11018157 | Local interconnect structure | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang +5 more | 2021-05-25 |