Issued Patents All Time
Showing 426–450 of 498 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6566250 | Method for forming a self aligned capping layer | Yeur-Luen Tu, Chih-Yang Pai | 2003-05-20 |
| 6555442 | Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer | Chih-Yang Pai, Chih-Hsing Yu, Yeur-Luen Tu, Min-hwa Chi | 2003-04-29 |
| 6514672 | Dry development process for a bi-layer resist system | Bao-Ju Young, Ying-Ying Wang | 2003-02-04 |
| 6501120 | Capacitor under bitline (CUB) memory cell structure employing air gap void isolation | Yeur-Luen Tu, Min-hwa Chi | 2002-12-31 |
| 6497993 | In situ dry etching procedure to form a borderless contact hole | Yuan-Hunh Chiu, Hun-Jan Tao, Chu-Yun Fu | 2002-12-24 |
| 6491042 | Post etching treatment process for high density oxide etcher | Bao-Ru Young | 2002-12-10 |
| 6486529 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Min-hwa Chi, Yeur-Luen Tu | 2002-11-26 |
| 6486025 | Methods for forming memory cell structures | Yuan-Hung Liu, Yeur-Luen Tu, Min-hwa Chi, Chih-Hsing Yu | 2002-11-26 |
| 6472335 | Methods of adhesion promoter between low-K layer and underlying insulating layer | Yao-Yi Cheng, Hun-Jan Tao | 2002-10-29 |
| 6429119 | Dual damascene process to reduce etch barrier thickness | Li-Chih Chao, Ming-Huei Lui, Jen-Cheng Liu, Chao-Cheng Chen | 2002-08-06 |
| 6417569 | Fluorine-doped silicate glass hard mask to improve metal line etching profile | Shau-Lin Shue | 2002-07-09 |
| 6399515 | Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity | Hun-Jan Tao | 2002-06-04 |
| 6399483 | Method for improving faceting effect in dual damascene process | Jen-Cheng Liu, Ming-Huei Lui, Hun-Jan Tao | 2002-06-04 |
| 6383943 | Process for improving copper fill integrity | Chao-Cheng Chen, Jen-Cheng Liu, Jyu-Horng Shieh, Bor-Shyang Lin | 2002-05-07 |
| 6362012 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Min-hwa Chi, Yeur-Luen Tu | 2002-03-26 |
| 6331480 | Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material | Yao-Yi Cheng, Hun-Jan Tao | 2001-12-18 |
| 6326296 | Method of forming dual damascene structure with improved contact/via edge integrity | Hun-Jan Tao | 2001-12-04 |
| 6323121 | Fully dry post-via-etch cleaning method for a damascene process | Jen-Cheng Liu, Chao-Cheng Chen, Li-Chih Chao, Ming-Huei Lui | 2001-11-27 |
| 6319822 | Process for forming an integrated contact or via | Chao-Cheng Chen, Shau-Lin Shue, Hun-Jan Tao | 2001-11-20 |
| 6319821 | Dual damascene approach for small geometry dimension | Jen-Cheng Liu, Chen-Cheng Kuo, Hung-Chang Hsieh | 2001-11-20 |
| 6316348 | High selectivity Si-rich SiON etch-stop layer | Chu-Yun Fu, Syun-Ming Jang | 2001-11-13 |
| 6309962 | Film stack and etching sequence for dual damascene | Chao-Cheng Chen, Li-Chi Chao, Jen-Cheng Liu, Min-Huei Lui | 2001-10-30 |
| 6271084 | Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process | Yeur-Luen Tu, Min-hwa Chi | 2001-08-07 |
| 6268287 | Polymerless metal hard mask etching | Bao-Ju Young, Ming-Hsin Huang | 2001-07-31 |
| 6255022 | Dry development process for a bi-layer resist system utilized to reduce microloading | Bao-Ju Young, Ying-Ying Wang | 2001-07-03 |