Issued Patents All Time
Showing 1,801–1,825 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6413863 | Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process | Chung-Shi Liu, Shau-Lin Shue | 2002-07-02 |
| 6403432 | Hardmask for a salicide gate process with trench isolation | Syun-Ming Jang | 2002-06-11 |
| 6403465 | Method to improve copper barrier properties | Chung-Shi Liu | 2002-06-11 |
| 6399487 | Method of reducing phase transition temperature by using silicon-germanium alloys | Jane-Bai Lai, Lih-Juan Chen, Chung-Shi Liu | 2002-06-04 |
| 6395642 | Method to improve copper process integration | Chung-Shi Liu | 2002-05-28 |
| 6383935 | Method of reducing dishing and erosion using a sacrificial layer | Cheng-Chung Lin, Tsu Shih, Weng Chang | 2002-05-07 |
| 6372664 | Crack resistant multi-layer dielectric layer and method for formation thereof | Syun-Ming Jang, Chu-Yun Fu | 2002-04-16 |
| 6372645 | Methods to reduce metal bridges and line shorts in integrated circuits | Chung-Shi Liu, Shau-Lin Shue, Shih-Chi Lin, Ming-Jer Lee, Ying-Lang Wang +1 more | 2002-04-16 |
| 6372632 | Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer | Weng Chang, Jih-Chung Twu, Tsu Shih | 2002-04-16 |
| 6372409 | Bonds pads equipped with heat dissipating rings and method for forming | — | 2002-04-16 |
| 6362085 | Method for reducing gate oxide effective thickness and leakage current | Mo Yu, Syun-Ming Jang | 2002-03-26 |
| 6361704 | Self stop aluminum pad for copper process | Tsu Shih | 2002-03-26 |
| 6353260 | Effective diffusion barrier | Chung-Shi Liu, Shau-Lin Shue | 2002-03-05 |
| 6350688 | Via RC improvement for copper damascene and beyond technology | Chung-Shi Liu, Shau-Lin Shue | 2002-02-26 |
| 6342448 | Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process | Jing-Cheng Lin, Shau-Lin Shue | 2002-01-29 |
| 6339029 | Method to form copper interconnects | Mong-Song Liang | 2002-01-15 |
| 6329717 | Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein | Syun-Ming Jang, Lung Chen, Lin-June Wu | 2001-12-11 |
| 6326300 | Dual damascene patterned conductor layer formation method | Chung-Shi Liu | 2001-12-04 |
| 6297158 | Stress management of barrier metal for resolving CU line corrosion | Chung-Shi Liu, Shau-Lin Shue | 2001-10-02 |
| 6287966 | Low sheet resistance of titanium salicide process | Chung-Shi Liu | 2001-09-11 |
| 6287961 | Dual damascene patterned conductor layer formation method without etch stop layer | Chung-Shi Liu | 2001-09-11 |
| 6277658 | Method for monitoring alignment mark shielding | Shwangming Jeng, Jeng-Horng Chen | 2001-08-21 |
| 6277745 | Passivation method of post copper dry etching | Chung-Shi Liu, Shau-Lin Shue, Syun-Ming Jang | 2001-08-21 |
| 6258715 | Process for low-k dielectric with dummy plugs | Shwangming Jeng | 2001-07-10 |
| 6255734 | Passivated copper line semiconductor device structure | Chung-Shi Liu | 2001-07-03 |