Issued Patents All Time
Showing 1,826–1,850 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6251777 | Thermal annealing method for forming metal silicide layer | Shwangming Jeng | 2001-06-26 |
| 6245691 | Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer | Syun-Ming Jang | 2001-06-12 |
| 6242356 | Etchback method for forming microelectronic layer with enhanced surface smoothness | Syun-Ming Jang, Chung-Long Chang, Shwangming Jeng | 2001-06-05 |
| 6242338 | Method of passivating a metal line prior to deposition of a fluorinated silica glass layer | Chung-Shi Liu, Shau-Lin Shue, Yao-Yi Cheng, Mei-Yun Wang | 2001-06-05 |
| 6239002 | Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer | Syun-Ming Jang, Ying-Ho Chen | 2001-05-29 |
| 6239023 | Method to reduce the damages of copper lines | Syun-Ming Jang, Ying-Ho Chen, Jih-Churng Twu | 2001-05-29 |
| 6232241 | Pre-oxidation cleaning method for reducing leakage current of ultra-thin gate oxide | Mo Yu | 2001-05-15 |
| 6228760 | Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish | Syun-Ming Jang, Tsu Shih, Anthony Yen, Jih-Churng Twu | 2001-05-08 |
| 6224737 | Method for improvement of gap filling capability of electrochemical deposition of copper | Ming-Hsing Tsai, Wen-Jye Tsai, Shau-Lin Shue | 2001-05-01 |
| 6225171 | Shallow trench isolation process for reduced for junction leakage | Syun-Ming Jang | 2001-05-01 |
| 6225223 | Method to eliminate dishing of copper interconnects | Chung-Shi Liu | 2001-05-01 |
| 6221758 | Effective diffusion barrier process and device manufactured thereby | Chung-Shi Liu, Shau-Lin Shue | 2001-04-24 |
| 6211075 | Method of improving metal stack reliability | Chung-Shi Liu, Shau-Lin Shue, Hung-Ju Chien | 2001-04-03 |
| 6211098 | Wet oxidation method for forming silicon oxide dielectric layer | Jih-Churng Twu, Syun-Ming Jang | 2001-04-03 |
| 6207568 | Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer | Chung-Shi Liu, Shau-Lin Shue | 2001-03-27 |
| 6197669 | Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process | Jih-Churng Twu, Syun-Ming Jang | 2001-03-06 |
| 6191025 | Method of fabricating a damascene structure for copper medullization | Chung-Shi Liu | 2001-02-20 |
| 6187663 | Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials | Syun-Ming Jang, Weng Chang, Yao-Yi Cheng | 2001-02-13 |
| 6187664 | Method for forming a barrier metallization layer | — | 2001-02-13 |
| 6181013 | Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby | Chung-Shi Liu, Tien-I Bao, Syun-Ming Jang | 2001-01-30 |
| 6177347 | In-situ cleaning process for Cu metallization | Chung-Shi Liu, Shau-Lin Shue | 2001-01-23 |
| 6171896 | Method of forming shallow trench isolation by HDPCVD oxide | Syun-Ming Jang, Ying-Ho Chen | 2001-01-09 |
| 6165052 | Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation | Syun-Ming Jang | 2000-12-26 |
| 6165898 | Dual damascene patterned conductor layer formation method without etch stop layer | Syun-Ming Jang | 2000-12-26 |
| 6162716 | Amorphous silicon gate with mismatched grain-boundary microstructure | Jih-Churng Twu | 2000-12-19 |