Issued Patents All Time
Showing 226–250 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8999805 | Semiconductor device with reduced gate length | Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo | 2015-04-07 |
| 8866235 | Source and drain dislocation fabrication in FinFETs | Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Ya-Yun Cheng +1 more | 2014-10-21 |
| 8669163 | Tunnel field-effect transistors with superlattice channels | Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee | 2014-03-11 |
| 8587075 | Tunnel field-effect transistor with metal source | Krishna Kumar Bhuwalka, Yi-Ming Sheu | 2013-11-19 |
| 8415749 | Semiconductor structure with dielectric-sealed doped region | Huan-Tsung Huang, Kou-Cheng Wu | 2013-04-09 |
| 8324090 | Method to improve dielectric quality in high-k metal gate technology | Yuri Masuoka, Peng-Fu Hsu, Huan-Tsung Huang, Kuo-Tai Huang, Yong-Tian Hou | 2012-12-04 |
| 8143680 | Gated diode with non-planar source region | Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung | 2012-03-27 |
| 7888191 | Forming floating body RAM using bulk silicon substrate | Ka-Hing Fung | 2011-02-15 |
| 7834345 | Tunnel field-effect transistors with superlattice channels | Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee | 2010-11-16 |
| 7768072 | Silicided metal gate for multi-threshold voltage configuration | Ching-Wei Tsai, Chih-Hao Wang, Wei-Jung Lin, Huan-Tsung Huang | 2010-08-03 |
| 7768099 | MIM capacitor integrated into the damascene structure and method of making thereof | Anthony Oates | 2010-08-03 |
| 7732877 | Gated diode with non-planar source region | Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung | 2010-06-08 |
| 7649228 | Forming floating body RAM using bulk silicon substrate | Ka-Hing Fung | 2010-01-19 |
| 7449753 | Write margin improvement for SRAM cells with SiGe stressors | Yin-Pin Wang | 2008-11-11 |
| 7429769 | Recessed channel field effect transistor (FET) device | Yi-Ming Sheu, Syun-Ming Jang, Hun-Jan Tao, Fu-Liang Yang | 2008-09-30 |
| 7342289 | Strained silicon MOS devices | Chien-Chao Huang, Chung-Hu Ge, Wen-Chin Lee, Chenming Hu, Fu-Liang Yang | 2008-03-11 |
| 7141459 | Silicon-on-insulator ULSI devices with multiple silicon film thicknesses | Fu-Liang Yang, Hao Chen, Yee-Chia Yeo, Chenming Hu | 2006-11-28 |
| 6974730 | Method for fabricating a recessed channel field effect transistor (FET) device | Yi-Ming Sheu, Syun-Ming Jang, Hun-Jan Tao, Fu-Liang Yang | 2005-12-13 |
| 6673683 | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions | Yi-Ming Sheu, Yi-Ling Chan, Da-Wen Lin, Wan-Yih Lien | 2004-01-06 |
| 6582995 | Method for fabricating a shallow ion implanted microelectronic structure | Ting-Hua Hsieh, Hung-Der Su | 2003-06-24 |
| 6548363 | Method to reduce the gate induced drain leakage current in CMOS devices | Chung-Cheng Wu, Bi-Ling Lin | 2003-04-15 |
| 6500739 | Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect | Howard Chih-Hao Wang, Su-Yu Lu, Mu-Chi Chiang | 2002-12-31 |
| 6391752 | Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane | Jean-Pierre Colinge | 2002-05-21 |
| 6380021 | Ultra-shallow junction formation by novel process sequence for PMOSFET | Jyh-Haur Wang, Chih-Chiang Wang, Hsien-Chin Lin, Kuo-Hua Pan | 2002-04-30 |
| 6368928 | Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects | Howard Chih-Hao Wang, Su-Yu Lu, Mu-Chi Chiang, Yu-Sen Chu, Chao-Jie Tsai | 2002-04-09 |