Issued Patents All Time
Showing 176–200 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754840 | Horizontal gate-all-around device having wrapped-around source and drain | Chun-Hsiung Lin, Chung-Cheng Wu, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu | 2017-09-05 |
| 9741821 | Two-step dummy gate formation | Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang, Ying-Keung Leung | 2017-08-22 |
| 9735146 | Vertical nanowire transistor for input/output structure | Jean-Pierre Colinge, Ta-Pen Guo | 2017-08-15 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu +1 more | 2017-08-15 |
| 9716096 | Semiconductor structure with feature spacer and method for manufacturing the same | Kuo-Cheng Ching, Chun-Hsiung Lin, Chih-Hao Wang, Ying-Keung Leung | 2017-07-25 |
| 9691695 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Ta-Pen Guo, Jean-Pierre Colinge, Yi-Hsiung Lin | 2017-06-27 |
| 9680012 | Semiconductor device structure and method for forming the same | Jean-Pierre Colinge, Jonathan Tsung-Yung Chang, Yue-Der Chih | 2017-06-13 |
| 9673209 | Memory device and method for fabricating the same | Jean-Pierre Colinge, Ta-Pen Guo | 2017-06-06 |
| 9660107 | 3D cross-bar nonvolatile memory | Jean-Pierre Colinge, Ta-Pen Guo | 2017-05-23 |
| 9659632 | SRAM with stacked bit cells | Ta-Pen Guo, Chih-Hao Wang, Jean-Pierre Colinge | 2017-05-23 |
| 9653604 | Semiconductor device and manufacturing method thereof | Jean-Pierre Colinge | 2017-05-16 |
| 9653457 | Stacked device and associated layout structure | Ta-Pen Guo, Chih-Hao Wang, Jean-Pierre Colinge | 2017-05-16 |
| 9640645 | Semiconductor device with silicide | Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo | 2017-05-02 |
| 9634091 | Silicon and silicon germanium nanowire formation | Kuo-Cheng Ching, Jean-Pierre Colinge | 2017-04-25 |
| 9627476 | Fin structure of semiconductor device | Chih-Hao Wang, Kuo-Cheng Ching, Zhiqiang Wu | 2017-04-18 |
| 9614086 | Conformal source and drain contacts for multi-gate field effect transistors | Yee-Chia Yeo, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun | 2017-04-04 |
| 9614091 | Gate structure and method for fabricating the same | Jean-Pierre Colinge, Ta-Pen Guo | 2017-04-04 |
| 9595443 | Metal gate structure of a semiconductor device | Ming Zhu, Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang +4 more | 2017-03-14 |
| 9589890 | Method for interconnect scheme | Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien +3 more | 2017-03-07 |
| 9570579 | Semiconductor structures and methods for multi-level work function | Jean-Pierre Colinge | 2017-02-14 |
| 9564431 | Semiconductor structures and methods for multi-level work function | Jean-Pierre Colinge, Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang | 2017-02-07 |
| 9564493 | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same | Jean-Pierre Colinge, Yee-Chia Yeo | 2017-02-07 |
| 9559181 | Structure and method for FinFET device with buried sige oxide | Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu | 2017-01-31 |
| 9543418 | Semiconductor liner of semiconductor device | Kuo-Cheng Ching, Chih-Hao Wang | 2017-01-10 |
| 9508858 | Contacts for highly scaled transistors | Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin +2 more | 2016-11-29 |