Issued Patents All Time
Showing 126–150 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10170404 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Ta-Pen Guo, Jean-Pierre Colinge, Yi-Hsiung Lin | 2019-01-01 |
| 10163729 | Silicon and silicon germanium nanowire formation | Kuo-Cheng Ching, Jean-Pierre Colinge | 2018-12-25 |
| 10164061 | Method of fabricating non-volatile memory device array | Jean-Pierre Colinge | 2018-12-25 |
| 10164040 | Gate structure and method for fabricating the same | Jean-Pierre Colinge, Ta-Pen Guo | 2018-12-25 |
| 10164033 | Conformal source and drain contacts for multi-gate field effect transistors | Yee-Chia Yeo, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun | 2018-12-25 |
| 10157999 | FinFET with a semiconductor strip as a base | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung | 2018-12-18 |
| 10157799 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung | 2018-12-18 |
| 10157928 | Semiconductor devices and methods of manufacture thereof | Jean-Pierre Colinge, Ta-Pen Guo | 2018-12-18 |
| 10141419 | Two-step dummy gate formation | Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang, Ying-Keung Leung | 2018-11-27 |
| 10134918 | Memory device and method for fabricating the same | Jean-Pierre Colinge, Ta-Pen Guo | 2018-11-20 |
| 10134915 | 2-D material transistor with vertical structure | Jean-Pierre Colinge, Chung-Cheng Wu, Chih-Hao Wang, Ken-Ichi Goto, Ta-Pen Guo +3 more | 2018-11-20 |
| 10109721 | Horizontal gate-all-around device having wrapped-around source and drain | Chun-Hsiung Lin, Chung-Cheng Wu, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu | 2018-10-23 |
| 10083869 | Stacked device and associated layout structure | Ta-Pen Guo, Chih-Hao Wang, Jean-Pierre Colinge | 2018-09-25 |
| 10062779 | Semiconductor device and manufacturing method thereof | Jean-Pierre Colinge | 2018-08-28 |
| 10032713 | Semiconductor device structure and method for forming the same | Yung-Chih Wang, Tien-Lu Lin | 2018-07-24 |
| 10026826 | Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric | Jean-Pierre Colinge, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu | 2018-07-17 |
| 10008414 | System and method for widening Fin widths for small pitch FinFET devices | Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung | 2018-06-26 |
| 10008253 | Array architecture and write operations of thyristor based random access memory | Yue-Der Chih, Jean-Pierre Colinge, Jonathan Tsung-Yung Chang | 2018-06-26 |
| 10008566 | Semiconductor device with reduced electrical resistance and capacitance | Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo | 2018-06-26 |
| 10000373 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Ken-Ichi Goto, Shau-Lin Shue, Tai-I Yang | 2018-06-19 |
| 10002922 | Process to etch semiconductor materials | Jean-Pierre Colinge, Mark van Dal | 2018-06-19 |
| 9978863 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo | 2018-05-22 |
| 9978853 | Method of forming gate structure of a semiconductor device | Ming Zhu, Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang +4 more | 2018-05-22 |
| 9947773 | Semiconductor arrangement with substrate isolation | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2018-04-17 |
| 9941404 | Tuning strain in semiconductor devices | Jean-Pierre Colinge, Kuo-Cheng Ching, Gwan Sin Chang, Zhiqiang Wu, Chih-Hao Wang | 2018-04-10 |