Issued Patents All Time
Showing 1–25 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9040356 | Semiconductor including cup-shaped leadframe packaging techniques | King Owyang, Yueh-Se Ho, Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2015-05-26 |
| 8169062 | Integrated circuit package for semiconductior devices with improved electric resistance and inductance | Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik Lui | 2012-05-01 |
| 8067822 | Integrated circuit package for semiconductor devices with improved electric resistance and inductance | Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik Lui | 2011-11-29 |
| 7863995 | Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS | Moses Ho, Madhur Bobde, Limin Weng | 2011-01-04 |
| 7633140 | Inverted J-lead for power devices | Leeshawn Luo, Anup Bhalla, Sik Lui, Yueh-Se Ho, Xiao Tiang Zhang | 2009-12-15 |
| 7595547 | Semiconductor die package including cup-shaped leadframe | King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2009-09-29 |
| 7391100 | Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area | Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik Lui | 2008-06-24 |
| 7208818 | Power semiconductor package | Leeshawn Luo, Anup Bhalla, Sik Lui, Yueh-Se Ho, Xiao Zhang | 2007-04-24 |
| 6909170 | Semiconductor assembly with package using cup-shaped lead-frame | King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2005-06-21 |
| 6841852 | Integrated circuit package for semiconductor devices with improved electric resistance and inductance | Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik Lui | 2005-01-11 |
| 6744124 | Semiconductor die package including cup-shaped leadframe | King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu | 2004-06-01 |
| 6509233 | Method of making trench-gated MOSFET having cesium gate oxide layer | Sik Lui, Sung-Shan Tai | 2003-01-21 |
| 6444527 | Method of operation of punch-through field effect transistor | Brian H. Floyd, Fwu-Iuan Hshieh | 2002-09-03 |
| 6277695 | Method of forming vertical planar DMOSFET with self-aligned contact | Richard K. Williams, Sung-Shan Tai, Dorman C. Pitzer, Wayne B. Grabowski, Anthony C. Tsui | 2001-08-21 |
| 6090716 | Method of fabricating a field effect transistor | Brian H. Floyd, Chin H. Ho, Min Juang, Brian Cheung, Karen Lee | 2000-07-18 |
| 6069043 | Method of making punch-through field effect transistor | Brian H. Floyd, Fwu-Iuan Hshieh | 2000-05-30 |
| 5998834 | Long channel trench-gated power MOSFET having fully depleted body region | Richard K. Williams, Brian H. Floyd, Wayne B. Grabowski, Mohamed N. Darwish | 1999-12-07 |
| 5981344 | Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon | Fwu-Iuan Hshieh | 1999-11-09 |
| 5929481 | High density trench DMOS transistor with trench bottom implant | Fwu-Iuan Hshieh, Brian H. Floyd, Danny Chi Nim, Daniel Ng | 1999-07-27 |
| 5923979 | Planar DMOS transistor fabricated by a three mask process | Dorman C. Pitzer, Hong-Xian Wang | 1999-07-13 |
| 5917216 | Trenched field effect transistor with PN depletion barrier | Brian H. Floyd, Dorman C. Pitzer, Fwu-Iuan Hshieh | 1999-06-29 |
| 5910669 | Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof | Fwu-Iuan Hshieh, Sze-Hon Kwan, King Owyang | 1999-06-08 |
| 5821583 | Trenched DMOS transistor with lightly doped tub | Fwu-Iuan Hshieh, Lih-Ying Ching, Hoang H. Tran | 1998-10-13 |
| 5770503 | Method of forming low threshold voltage vertical power transistor using epitaxial technology | Fwu-Iuan Hshieh, Hamza Yilmaz | 1998-06-23 |
| 5767578 | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation | King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho, Jowei Dun, Hans-Jurgen Fusser +1 more | 1998-06-16 |