Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768274 | Laterally-graded doping of materials | Kuo-Chang Yang, Kamal Raj Varadarajan, Sujit Banerjee, Vijay Parthasarathy | 2017-09-19 |
| 9472630 | Deposit/etch for tapered oxide | Vijay Parthasarathy, Sujit Banerjee | 2016-10-18 |
| 8765609 | Deposit/etch for tapered oxide | Vijay Parthasarathy, Sujit Banerjee | 2014-07-01 |
| 8552493 | Segmented pillar layout for a high-voltage vertical transistor | Vijay Parthasarathy | 2013-10-08 |
| 7816731 | Segmented pillar layout for a high-voltage vertical transistor | Vijay Parthasarathy | 2010-10-19 |
| 7557406 | Segmented pillar layout for a high-voltage vertical transistor | Vijay Parthasarathy | 2009-07-07 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same | Richard K. Williams | 2007-10-16 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same | Richard K. Williams | 2007-10-02 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same | Richard K. Williams | 2007-07-03 |
| 7115958 | Lateral power MOSFET for high switching speeds | Donald R. Disney | 2006-10-03 |
| 7052963 | Method of forming trench transistor with chained implanted body including a plurality of implantation with different energies | Richard K. Williams | 2006-05-30 |
| 6924198 | Self-aligned trench transistor using etched contact | Richard K. Williams | 2005-08-02 |
| 6900100 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same | Richard K. Williams | 2005-05-31 |
| 6825536 | Lateral power MOSFET for high switching speeds | Donald R. Disney | 2004-11-30 |
| 6756274 | Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance | Richard K. Williams | 2004-06-29 |
| 6750507 | Super-self-aligned trench-gated DMOS with reduced on-resistance | Richard K. Williams | 2004-06-15 |
| 6555883 | Lateral power MOSFET for high switching speeds | Donald R. Disney | 2003-04-29 |
| 6413822 | Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer | Richard K. Williams | 2002-07-02 |
| 6291298 | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses | Richard K. Williams | 2001-09-18 |
| 6277695 | Method of forming vertical planar DMOSFET with self-aligned contact | Richard K. Williams, Sung-Shan Tai, Dorman C. Pitzer, Anthony C. Tsui, Mike F. Chang | 2001-08-21 |
| 6268242 | Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact | Richard K. Williams | 2001-07-31 |
| 6239463 | Low resistance power MOSFET or other device containing silicon-germanium layer | Richard K. Williams, Mohamed N. Darwish, Michael E. Cornell | 2001-05-29 |
| 6204533 | Vertical trench-gated power MOSFET having stripe geometry and high cell density | Richard K. Williams | 2001-03-20 |
| 6140678 | Trench-gated power MOSFET with protective diode | Richard K. Williams, Mohamed N. Darwish | 2000-10-31 |
| 6078090 | Trench-gated Schottky diode with integral clamping diode | Richard K. Williams, Shekar S. Malikarjunaswamy, Jacek Korec | 2000-06-20 |