Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10644118 | Self-aligned contact for trench power MOSFET | Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li +1 more | 2020-05-05 |
| 10424654 | Power device with high aspect ratio trench contacts and submicron pitches between trenches | Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang +2 more | 2019-09-24 |
| 10020380 | Power device with high aspect ratio trench contacts and submicron pitches between trenches | Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang +2 more | 2018-07-10 |
| 9691863 | Self-aligned contact for trench power MOSFET | Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li +1 more | 2017-06-27 |
| 6479881 | Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry | Ying-Lang Wang, Chun-Ching Tsan, Hung-Ju Chien | 2002-11-12 |
| 6395635 | Reduction of tungsten damascene residue | Ying-Lang Wang | 2002-05-28 |
| 6291331 | Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue | Ying-Lang Wang, Ming-Jer Lee, Tong-Hua Kuan | 2001-09-18 |
| 6291872 | Three-dimensional type inductor for mixed mode radio frequency device | Ying-Lang Wang, Hway-Chi Lin, Jun Wu | 2001-09-18 |
| 6281146 | Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity | Ying-Lang Wang, Hui Wang, Szu-An Wu | 2001-08-28 |
| 6268274 | Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry | Ying-Lang Wang, Chun-Ching Tsan, Hung-Ju Chien | 2001-07-31 |
| 6099662 | Process for cleaning a semiconductor substrate after chemical-mechanical polishing | Ying-Lang Wang, Ken-Shen Chou, Yu-Ku Lin | 2000-08-08 |
| 5956609 | Method for reducing stress and improving step-coverage of tungsten interconnects and plugs | Jiun-Chung Lee, Hui Wang, Ken-Shen Chou | 1999-09-21 |
| 5904525 | Fabrication of high-density trench DMOS using sidewall spacers | Fwu-Iuan Hshieh, Yueh-Se Ho, Bosco Lan | 1999-05-18 |
| 5767578 | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation | Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho, Hans-Jurgen Fusser +1 more | 1998-06-16 |
| 5757081 | Surface mount and flip chip technology for total integrated circuit isolation | Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho | 1998-05-26 |
| 5753529 | Surface mount and flip chip technology for total integrated circuit isolation | Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho | 1998-05-19 |
| 5284800 | Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor process | Chuen-Der Lien, Daniel Liao | 1994-02-08 |