Issued Patents All Time
Showing 76–100 of 256 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10726926 | Hot-cold VTH mismatch using VREAD modulation | Dae Wung Kang, Peter Rabkin | 2020-07-28 |
| 10658381 | Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same | Jixin Yu, Fumiaki Toyama, Tong Zhang, Chun Ge, Xin Li +1 more | 2020-05-19 |
| 10650898 | Erase operation in 3D NAND flash memory including pathway impedance compensation | Peter Rabkin, Kwang Ho Kim, Yingda Dong | 2020-05-12 |
| 10510738 | Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof | Kwang Ho Kim, Fumiaki Toyama, Akio Nishida | 2019-12-17 |
| 10319680 | Metal contact via structure surrounded by an air gap and method of making thereof | Jongsun Sel, Mohan Dunga, Fumiaki Toyama, Peter Rabkin | 2019-06-11 |
| 10297329 | NAND boosting using dynamic ramping of word line voltages | Peter Rabkin, Yingda Dong | 2019-05-21 |
| 10115459 | Multiple liner interconnects for three dimensional memory devices and method of making thereof | Katsuo Yamada, Tomoyasu Kakegawa, Peter Rabkin, Jayavel Pachamuthu, Mohan Dunga | 2018-10-30 |
| 10103161 | Offset backside contact via structures for a three-dimensional memory device | Fumitoshi Ito, Cheng-Chung Chu, Jayavel Pachamuthu, Tuan Pham | 2018-10-16 |
| 9941295 | Method of making a three-dimensional memory device having a heterostructure quantum well channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2018-04-10 |
| 9929174 | Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making thereof | Yuki Mizutani, Hiroyuki Ogawa, Fumiaki Toyama, Fumitaka Amano, Kota Funayama +1 more | 2018-03-27 |
| 9917093 | Inter-plane offset in backside contact via structures for a three-dimensional memory device | Cheng-Chung Chu, Jayavel Pachamuthu, Tuan Pham, Fumitoshi Ito | 2018-03-13 |
| 9876025 | Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2018-01-23 |
| 9818801 | Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof | Peter Rabkin, Perumal Ratnam, Christopher J. Petti | 2017-11-14 |
| 9780108 | Ultrathin semiconductor channel three-dimensional memory devices | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2017-10-03 |
| 9761604 | 3D vertical NAND with III-V channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2017-09-12 |
| 9721963 | Three-dimensional memory device having a transition metal dichalcogenide channel | Peter Rabkin | 2017-08-01 |
| 9711229 | 3D NAND with partial block erase | Peter Rabkin | 2017-07-18 |
| 9685484 | Reversible resistivity memory with crystalline silicon bit line | Peter Rabkin, Perumal Ratnam, Chris Petti | 2017-06-20 |
| 9685454 | Method of forming 3D vertical NAND with III-V channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2017-06-20 |
| 9634097 | 3D NAND with oxide semiconductor channel | Peter Rabkin, Johann Alsmeier | 2017-04-25 |
| 9613975 | Bridge line structure for bit line connection in a three-dimensional semiconductor device | Chenche Huang, Chun-Ming Wang, Yuki Mizutani, Hiroaki Koketsu, Masayuki Hiroi | 2017-04-04 |
| 9564226 | Smart verify for programming non-volatile memory | Mohan Dunga, Gerrit Jan Hemink, Zhenming Zhou | 2017-02-07 |
| 9563504 | Partial block erase for data refreshing and open-block programming | Guirong Liang, Zhenming Zhou | 2017-02-07 |
| 9530504 | Memory cells using multi-pass programming | Bo Lei, Gerrit Jan Hemink, Jun Wan, Zhenming Zhou | 2016-12-27 |
| 9530506 | NAND boosting using dynamic ramping of word line voltages | Peter Rabkin, Yingda Dong | 2016-12-27 |