Issued Patents All Time
Showing 126–150 of 256 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9142302 | Efficient smart verify method for programming 3D non-volatile memory | Yingda Dong, Cynthia Hsu, Man Lung Mui, Manabu Sakai, Toru Miwa | 2015-09-22 |
| 9142298 | Efficient smart verify method for programming 3D non-volatile memory | Yingda Dong, Cynthia Hsu, Man Lung Mui, Manabu Sakai, Toru Miwa | 2015-09-22 |
| 9142305 | System to reduce stress on word line select transistor during erase operation | Mohan Dunga, Man Lung Mui, Fumiaki Toyama | 2015-09-22 |
| 9142304 | Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current | Xiying Costa, Haibo Li, Man Lung Mui | 2015-09-22 |
| 9129681 | Thin film transistor | Peter Rabkin | 2015-09-08 |
| 9123420 | 3D non-volatile storage with transistor decoding structure | Peter Rabkin | 2015-09-01 |
| 9123425 | Adjusting control gate overdrive of select gate transistors during programming of non-volatile memory | Yingda Dong | 2015-09-01 |
| 9105468 | Vertical bit line wide band gap TFT decoder | Peter Rabkin | 2015-08-11 |
| 9087601 | Select gate bias during program of non-volatile storage | Deepanshu Dutta, Shinji Sato, Fumiko Yano, Chun-Hung Lai | 2015-07-21 |
| 9082502 | Bit line and compare voltage modulation for sensing nonvolatile storage elements | Mohan Dunga | 2015-07-14 |
| 9053810 | Defect or program disturb detection with full data recovery capability | Deepanshu Dutta, Dana Lee, Yan Li, Grishma Shah, Farookh Moogat | 2015-06-09 |
| 9019775 | Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current | Xiying Costa, Haibo Li, Man Lung Mui | 2015-04-28 |
| 9013928 | Dynamic bit line bias for programming non-volatile memory | Deepanshu Dutta, Ken Oowada, Man Lung Mui | 2015-04-21 |
| 8988917 | Bit line resistance compensation | Kwang Ho Kim, Fumiaki Toyama, Seungpil Lee | 2015-03-24 |
| 8982637 | Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memory | Yingda Dong, Chenfeng Zhang, Wendy Ou, Seung Yu | 2015-03-17 |
| 8982629 | Method and apparatus for program and erase of select gate transistors | Deepanshu Dutta, Yan Li, Mohan Dunga | 2015-03-17 |
| 8982626 | Program and read operations for 3D non-volatile memory based on memory hole diameter | Yingda Dong, Wendy Ou, Man Lung Mui | 2015-03-17 |
| 8964473 | Select gate materials having different work functions in non-volatile memory | Yingda Dong | 2015-02-24 |
| 8958249 | Partitioned erase and erase verification in non-volatile memory | Deepanshu Dutta, Chun-Hung Lai, Shih-Chung Lee, Ken Oowada | 2015-02-17 |
| 8956968 | Method for fabricating a metal silicide interconnect in 3D non-volatile memory | Peter Rabkin | 2015-02-17 |
| 8953386 | Dynamic bit line bias for programming non-volatile memory | Deepanshu Dutta, Ken Oowada, Man Lung Mui | 2015-02-10 |
| 8951859 | Method for fabricating passive devices for 3D non-volatile memory | Peter Rabkin | 2015-02-10 |
| 8946022 | Integrated nanostructure-based non-volatile memory fabrication | Vinod R. Purayath, James Kai, Takashi Orimoto, George Matamis, Henry Chien | 2015-02-03 |
| 8937837 | Bit line BL isolation scheme during erase operation for non-volatile storage | Mohan Dunga, Kwang Ho Kim | 2015-01-20 |
| 8933502 | 3D non-volatile memory with metal silicide interconnect | Peter Rabkin | 2015-01-13 |