Issued Patents All Time
Showing 151–175 of 256 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8929142 | Programming select gate transistors and memory cells using dynamic verify level | Yingda Dong, Cynthia Hsu, Ken Oowada | 2015-01-06 |
| 8923048 | 3D non-volatile storage with transistor decoding structure | Peter Rabkin | 2014-12-30 |
| 8917554 | Back-biasing word line switch transistors | Fumiaki Toyama | 2014-12-23 |
| 8913432 | Programming select gate transistors and memory cells using dynamic verify level | Yingda Dong, Cynthia Hsu, Ken Oowada | 2014-12-16 |
| 8908441 | Double verify method in multi-pass programming to suppress read noise | Deepanshu Dutta, Ken Oowada, Genki Sano | 2014-12-09 |
| 8902668 | Double verify method with soft programming to suppress read noise | Deepanshu Dutta, Ken Oowada, Genki Sano | 2014-12-02 |
| 8891308 | Dynamic erase voltage step size selection for 3D non-volatile memory | Wendy Ou, Man Lung Mui, Yingda Dong | 2014-11-18 |
| 8885404 | Non-volatile storage system with three layer floating gate | Deepanshu Dutta, Shinji Sato, Dengtao Zhao, Sanghyun Lee | 2014-11-11 |
| 8885418 | Adaptive double pulse BCF programming | Sung-Yong Chung, Uday Chandrasekhar, Jianmin Huang | 2014-11-11 |
| 8877627 | Method of forming PN floating gate non-volatile storage elements and transistor having N+ gate | Mohan Dunga, Sanghyun Lee, Tuan Pham | 2014-11-04 |
| 8879333 | Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits | Xiying Costa, Haibo Li, Man Lung Mui | 2014-11-04 |
| 8873293 | Dynamic erase voltage step size selection for 3D non-volatile memory | Wendy Ou, Man Lung Mui, Yingda Dong | 2014-10-28 |
| 8865535 | Fabricating 3D non-volatile storage with transistor decoding structure | Peter Rabkin | 2014-10-21 |
| 8867271 | Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device | Haibo Li, Xiying Costa, Man Lung Mui | 2014-10-21 |
| 8861282 | Method and apparatus for program and erase of select gate transistors | Deepanshu Dutta, Yan Li, Mohan Dunga | 2014-10-14 |
| 8853763 | Integrated circuits with sidewall nitridation | Tuan Pham, Sanghyun Lee, Masato Horiike, Klaus Schuegraf, Keiichi Isono | 2014-10-07 |
| 8837216 | Non-volatile storage system with shared bit lines connected to a single selection device | Nima Mokhlesi, Mohan Dunga | 2014-09-16 |
| 8797800 | Select gate materials having different work functions in non-volatile memory | Yingda Dong | 2014-08-05 |
| 8787094 | Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits | Xiying Costa, Haibo Li, Man Lung Mui | 2014-07-22 |
| 8765552 | Non-volatile storage having a connected source and well | — | 2014-07-01 |
| 8658335 | Method of patterning NAND strings using perpendicular SRAF | Chen-Che Huang, Chun-Ming Wang | 2014-02-25 |
| 8643142 | Passive devices for 3D non-volatile memory | Peter Rabkin | 2014-02-04 |
| 8551839 | Non-volatile storage with substrate cut-out and process of fabricating | — | 2013-10-08 |
| 8547720 | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | George Samachisa, Luca Fasoli, Roy E. Scheuerlein | 2013-10-01 |
| 8503229 | P-/Metal floating gate non-volatile storage element | Sanghyun Lee, Mohan Dunga, Tuan Pham, Franz Kreupl | 2013-08-06 |