Issued Patents All Time
Showing 51–75 of 256 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11164883 | Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same | Peter Rabkin, Jayavel Pachamuthu | 2021-11-02 |
| 11133297 | Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof | Kwang Ho Kim, Fumiaki Toyama, Akio Nishida | 2021-09-28 |
| 11107516 | Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same | Peter Rabkin | 2021-08-31 |
| 11101284 | Three-dimensional memory device containing etch stop structures and methods of making the same | Jayavel Pachamuthu, Hiroyuki Kinoshita, Makoto Dei, Junji Oh | 2021-08-24 |
| 11094653 | Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same | Chen Wu, Peter Rabkin, Yangyin Chen | 2021-08-17 |
| 11088116 | Bonded assembly containing horizontal and vertical bonding interfaces and methods of forming the same | Chen Wu, Peter Rabkin | 2021-08-10 |
| 11074976 | Temperature dependent impedance mitigation in non-volatile memory | Peter Rabkin, Kwang Ho Kim | 2021-07-27 |
| 11037908 | Bonded die assembly containing partially filled through-substrate via structures and methods for making the same | Chen Wu, Peter Rabkin, Yangyin Chen | 2021-06-15 |
| 11031088 | Hot-cold VTH mismatch using VREAD modulation | Dae Wung Kang, Peter Rabkin | 2021-06-08 |
| 11004773 | Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same | Chen Wu, Peter Rabkin | 2021-05-11 |
| 11004518 | Threshold voltage setting with boosting read scheme | Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada | 2021-05-11 |
| 10991721 | Three-dimensional memory device including liner free molybdenum word lines and methods of making the same | Peter Rabkin, Raghuveer S. Makala | 2021-04-27 |
| 10957401 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada | 2021-03-23 |
| 10950311 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada | 2021-03-16 |
| 10923196 | Erase operation in 3D NAND | Peter Rabkin, Kwang Ho Kim | 2021-02-16 |
| 10910064 | Location dependent impedance mitigation in non-volatile memory | Peter Rabkin, Kwang Ho Kim | 2021-02-02 |
| 10903222 | Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same | Kiyohiko Sakakibara, Masanori Tsutsumi, Zhixin Cui | 2021-01-26 |
| 10847452 | Non-volatile memory with capacitors using metal under signal line or above a device capacitor | Luisa Lin, Mohan Dunga, Venkatesh Ramachandra, Peter Rabkin | 2020-11-24 |
| 10840260 | Through-array conductive via structures for a three-dimensional memory device and methods of making the same | James Kai, Murshed Chowdhury, Fumiaki Toyama, Johann Alsmeier | 2020-11-17 |
| 10840259 | Three-dimensional memory device including liner free molybdenum word lines and methods of making the same | Peter Rabkin, Raghuveer S. Makala | 2020-11-17 |
| 10825827 | Non-volatile memory with pool capacitor | Mohan Dunga, James Kai, Venkatesh Ramachandra, Piyush Dak, Luisa Lin | 2020-11-03 |
| 10818685 | Non-volatile memory with pool capacitor | Mohan Dunga, James Kai, Venkatesh Ramachandra, Piyush Dak, Luisa Lin | 2020-10-27 |
| 10789992 | Non-volatile memory with capacitors using metal under pads | Luisa Lin, Mohan Dunga, Venkatesh Ramachandra, Peter Rabkin | 2020-09-29 |
| 10763271 | Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same | Peter Rabkin, Jayavel Pachamuthu | 2020-09-01 |
| 10755788 | Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses | Peter Rabkin, Kwang Ho Kim, Yingda Dong | 2020-08-25 |