Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11482528 | Pillar capacitor and method of fabricating such | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-10-25 |
| 11469327 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-10-11 |
| 11462411 | Gate contact over active regions | Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sanjay Natarajan, Sean M. Seutter +1 more | 2022-10-04 |
| 11444203 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-09-13 |
| 11430861 | Ferroelectric capacitor and method of patterning such | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-08-30 |
| 11417768 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-08-16 |
| 11411116 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-08-09 |
| 11398570 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-07-26 |
| 11381244 | Low power ferroelectric based majority logic gate multiplier | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more | 2022-07-05 |
| 11374574 | Linear input and non-linear output threshold logic gate | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more | 2022-06-28 |
| 11355643 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-06-07 |
| 11349031 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-05-31 |
| 11328928 | Conformal high concentration boron doping of semiconductors | Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy +2 more | 2022-05-10 |
| 11296708 | Low power ferroelectric based majority logic gate adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more | 2022-04-05 |
| 11296228 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-04-05 |
| 11289608 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-03-29 |
| 11289607 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2022-03-29 |
| 11289497 | Integration method of ferroelectric memory array | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-03-29 |
| 11283453 | Low power ferroelectric based majority logic gate carry propagate and serial adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more | 2022-03-22 |
| 11211286 | Airgap formation processes | Ashish Pal, Sankuei Lin, Ching-Mei Hsu, Nitin K. Ingle, Ajay Bhatnagar +1 more | 2021-12-28 |
| 11195923 | Method of fabricating a semiconductor device having reduced contact resistance | Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Mandrekar, Andy Lo +3 more | 2021-12-07 |
| 11171058 | Self-aligned 3-D epitaxial structures for MOS device fabrication | Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Tahir Ghani | 2021-11-09 |
| 11165430 | Majority logic gate based sequential circuit | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more | 2021-11-02 |
| 11164976 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Sasikanth Manipatruni | 2021-11-02 |
| 11152221 | Methods and apparatus for metal silicide deposition | Xuebin Li, Wei Liu, Shashank Sharma, Patricia M. Liu, Schubert S. Chu | 2021-10-19 |