Issued Patents All Time
Showing 25 most recent of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9252146 | Work function adjustment by carbon implant in semiconductor devices including gate structure | Yue Liang, Dechao Guo, Shreesh Narasimha, Yanfeng Wang | 2016-02-02 |
| 9082877 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, Brian J. Greene, Unoh Kwon, Shreesh Narasimha +1 more | 2015-07-14 |
| 9040399 | Threshold voltage adjustment for thin body MOSFETs | MaryJane Brodsky, Ming Cai, Dechao Guo, Shreesh Narasimha, Yue Liang +3 more | 2015-05-26 |
| 8962417 | Method and structure for pFET junction profile with SiGe channel | Kern Rim, Yue Liang, Xinlin Wang | 2015-02-24 |
| 8946721 | Structure and method for using high-K material as an etch stop layer in dual stress layer process | — | 2015-02-03 |
| 8803243 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, Brian J. Greene, Unoh Kwon, Shreesh Narasimha +1 more | 2014-08-12 |
| 8728925 | Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG) | Michael P. Chudzik, Unoh Kwon | 2014-05-20 |
| 8729637 | Work function adjustment by carbon implant in semiconductor devices including gate structure | Yue Liang, Dechao Guo, Shreesh Narasimha, Yanfeng Wang | 2014-05-20 |
| 8673757 | Structure and method for using high-k material as an etch stop layer in dual stress layer process | — | 2014-03-18 |
| 8659054 | Method and structure for pFET junction profile with SiGe channel | Kern Rim, Yue Liang, Xinlin Wang | 2014-02-25 |
| 8598009 | Self-aligned embedded SiGe structure and method of manufacturing the same | Brian J. Greene, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal +1 more | 2013-12-03 |
| 8575709 | High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof | Huiming Bu, Michael P. Chudzik, Wei He, Siddarth A. Krishnan, Unoh Kwon +2 more | 2013-11-05 |
| 8507992 | High-K metal gate CMOS | Renee T. Mo, Huiming Bu, Michael P. Chudzik, Mukesh V. Khare, Vijay Narayanan | 2013-08-13 |
| 8354309 | Method of providing threshold voltage adjustment through gate dielectric stack modification | Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, Yue Liang, Edward P. Maciejewski +3 more | 2013-01-15 |
| 8350341 | Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG) | Michael P. Chudzik, Unoh Kwon | 2013-01-08 |
| 8318565 | High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof | Huiming Bu, Michael P. Chudzik, Wei He, Siddarth A. Krishnan, Unoh Kwon +2 more | 2012-11-27 |
| 8299570 | Efuse containing sige stack | Deok-kee Kim, Dureseti Chidambarrao, Chandrasekharan Kothandaraman | 2012-10-30 |
| 8268698 | Formation of improved SOI substrates using bulk semiconductor wafers | Dureseti Chidambarrao, Kern Rim, Hsingjen Wann, Hung Y. Ng | 2012-09-18 |
| 8232606 | High-K dielectric and metal gate stack with minimal overlap with isolation region | Michael P. Chudzik, Renee T. Mo, Jeffrey W. Sleight | 2012-07-31 |
| 8227870 | Method and structure for gate height scaling with high-k/metal gate technology | Michael P. Chudzik, Ricardo A. Donaton, Yue Liang | 2012-07-24 |
| 8222673 | Self-aligned embedded SiGe structure and method of manufacturing the same | Brian J. Greene, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal +1 more | 2012-07-17 |
| 8138037 | Method and structure for gate height scaling with high-k/metal gate technology | Michael P. Chudzik, Ricardo A. Donaton, Yue Liang | 2012-03-20 |
| 8106455 | Threshold voltage adjustment through gate dielectric stack modification | Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, Yue Liang, Edward P. Maciejewski +3 more | 2012-01-31 |
| 8030709 | Metal gate stack and semiconductor gate stack for CMOS devices | Charlotte DeWan Adams, Bruce B. Doris, Philip A. Fisher, Jeffrey W. Sleight | 2011-10-04 |
| 8021939 | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods | Michael P. Chudzik, Renee T. Mo, Jeffrey W. Sleight | 2011-09-20 |