Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423106 | Next fetch predictor for trace cache | Muawya M. Al-Otoom, Pruthivi Vuyyuru | 2025-09-23 |
| 12373215 | Using a next fetch predictor circuit with short branches and return fetch groups | Mary D. Brown, Ethan Schuchman, Ronald P. Hall, Ian D. Kountanis, Douglas C. Holman +3 more | 2025-07-29 |
| 12353882 | Next fetch prediction using history | Pruthivi Vuyyuru, Ilhyun Kim, Ian D. Kountanis | 2025-07-08 |
| 12326819 | Renaming context identifiers in a processor | John D. Pape, Madhu Sudan Har | 2025-06-10 |
| 12321751 | Re-use of speculative control transfer instruction results from wrong path | Yuan C. Chou, Deepankar Duggal, Debasish Chandra, Richard F. Russo | 2025-06-03 |
| 12265823 | Trace cache with filter for internal control transfer inclusion | Ilhyun Kim, Muawya M. Al-Otoom, Pruthivi Vuyyuru, Ronald P. Hall | 2025-04-01 |
| 12236244 | Multi-degree branch predictor | Wei-Han Lien, Muawya M. Al-Otoom, Ian D. Kountanis, Pruthivi Vuyyuru | 2025-02-25 |
| 12229561 | Processing of data synchronization barrier instructions | Madhu Sudan Hari, Mridul Agarwal, Kulin N. Kothari, John D. Pape | 2025-02-18 |
| 12175248 | Re-use of speculative load instruction results from wrong path | Yuan C. Chou, Deepankar Duggal, Debasish Chandra, Richard F. Russo | 2024-12-24 |
| 12067399 | Conditional instructions prediction | Ian D. Kountanis, Douglas C. Holman, Wei-Han Lien, Pruthivi Vuyyuru, Ethan Schuchman +2 more | 2024-08-20 |
| 11809874 | Conditional instructions distribution and execution on pipelines having different latencies for mispredictions | Ethan Schuchman, Kulin N. Kothari, Haoyan Jia, Ian D. Kountanis, Douglas C. Holman +2 more | 2023-11-07 |
| 11550723 | Method, apparatus, and system for memory bandwidth aware data prefetching | David Scott Ray, Thomas Philip Speier, Eric F. Robinson, Harold W. Cain, III, Nikhil Narendradev Sharma +3 more | 2023-01-10 |
| 11061822 | Method, apparatus, and system for reducing pipeline stalls due to address translation misses | Pritha Ghoshal, Ravi Rajagopalan, Patrick Eibl, Brian Michael Stempel, David Scott Ray +1 more | 2021-07-13 |
| 10877895 | Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions | Luke Yen, Pritha Ghoshal, Thomas Philip Speier, Brian Michael Stempel, William James McAvoy +1 more | 2020-12-29 |
| 9471325 | Method and apparatus for selective renaming in a microprocessor | Anil Krishna, Sandeep Suresh Navada, Michael Scott McIlvaine, Thomas Andrew Sartorius, Rodney Wayne Smith +1 more | 2016-10-18 |