Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8362537 | Memory devices including semiconductor pillars | Peter Baars | 2013-01-29 |
| 7482110 | Method for adapting structure dimensions during the photolithographic projection of a pattern of structure elements onto a semiconductor wafer | — | 2009-01-27 |
| 7465522 | Photolithographic mask having half tone main features and perpendicular half tone assist features | Lothar Bauch, Hermann Sachse, Helmut Wurzer | 2008-12-16 |
| 7462426 | Method for producing a phase mask | Wolfgang Henke | 2008-12-09 |
| 7248351 | Optimizing light path uniformity in inspection systems | William Roberts, Patrick Lomtscher, Karl-Heinz Schumacher | 2007-07-24 |
| 7074529 | Phase-shift mask | Shahid Butt | 2006-07-11 |
| 6911687 | Buried bit line-field isolation defined active semiconductor areas | Jack A. Mandelman | 2005-06-28 |
| 6842222 | Method of reducing pitch on semiconductor wafer | Shahid Butt, Alan C. Thomas, Juergen Preuninger | 2005-01-11 |
| 6809800 | Apparatus for patterning a semiconductor wafer | Oliver Genz, Jurgen Preuninger | 2004-10-26 |
| 6727989 | Enhanced overlay measurement marks for overlay alignment and exposure tool condition control | Xiaoming Yin, Christopher Gould | 2004-04-27 |
| 6606151 | Grating patterns and method for determination of azimuthal and radial aberration | Shahid Butt, Joseph P. Kirk | 2003-08-12 |
| 6590657 | Semiconductor structures and manufacturing methods | Christian Summerer, Shahid Butt, Uwe Schroeder | 2003-07-08 |
| 6566219 | Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening | Shahid Butt, Ramachandra Divakaruni, Armin Reith, Munir D. Naeem | 2003-05-20 |
| 6558883 | Apparatus and method for patterning a semiconductor wafer | Oliver Genz, Jurgen Preuninger | 2003-05-06 |
| 6511791 | Multiple exposure process for formation of dense rectangular arrays | Scott Bukofsky, Richard J. Wise, Alfred Wong | 2003-01-28 |
| 6451508 | Plural interleaved exposure process for increased feature aspect ratio in dense arrays | Scott Bukofsky, Alan C. Thomas | 2002-09-17 |
| 6420272 | Method for removal of hard mask used to define noble metal electrode | Hua Shen, David E. Kotecki, Satish D. Athavale, Jenny Lian, Nimal Chaudhary | 2002-07-16 |
| 6383691 | Photomask and method for increasing image aspect ratio while relaxing mask fabrication requirements | Mihel Seitz | 2002-05-07 |
| 6379869 | Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning | Uwe Schroeder, Alois Gutmann, Bruno Spuler | 2002-04-30 |
| 6365328 | Semiconductor structure and manufacturing method | Hua Shen, David E. Kotecki, Satish D. Athavale, Jenny Lian, Laertis Economikos +2 more | 2002-04-02 |
| 6282116 | Dynamic random access memory | Shahid Butt, Carl Radens | 2001-08-28 |
| 6211544 | Memory cell layout for reduced interaction between storage nodes and transistors | Young Jin Park, Carl Radens | 2001-04-03 |
| 6136660 | Stacked capacitator memory cell and method of fabrication | Hua Shen, Martin Gutsche | 2000-10-24 |
| 6118683 | Dynamic random access memory cell layout | Shahid Butt, Carl Radens | 2000-09-12 |
| 6083788 | Stacked capacitor memory cell and method of manufacture | Jenny Lian | 2000-07-04 |