Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8940554 | Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness | Nathaniel Berliner, Kangguo Cheng, Toshiharu Furukawa, William R. Tonti | 2015-01-27 |
| 8900885 | Wafer bonding misalignment reduction | Alex Richard Hubbard, Spyridon Skordas, Kevin R. Winstel | 2014-12-02 |
| 8871624 | Sealed air gap for semiconductor chip | David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Shom Ponoth | 2014-10-28 |
| 8765578 | Edge protection of bonded wafers during wafer thinning | Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel | 2014-07-01 |
| 8647939 | Non-relaxed embedded stressors with solid source extension regions in CMOS devices | Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz | 2014-02-11 |
| 8637953 | Wafer scale membrane for three-dimensional integrated circuit device fabrication | Sampath Purushothaman, James Vichiconti | 2014-01-28 |
| 8637358 | Field-effect-transistor with self-aligned diffusion contact | Charles W. Koburger, III | 2014-01-28 |
| 8592270 | Non-relaxed embedded stressors with solid source extension regions in CMOS devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni | 2013-11-26 |
| 8390079 | Sealed air gap for semiconductor chip | David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Shom Ponoth | 2013-03-05 |
| 8232618 | Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach | Gregory Breyta, David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Shom Ponoth | 2012-07-31 |
| 8124427 | Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness | Nathaniel Berliner, Kangguo Cheng, Toshiharu Furukawa, William R. Tonti | 2012-02-28 |
| 7955967 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias | Mark Todhunter Robson | 2011-06-07 |
| 7875528 | Method, system, program product for bonding two circuitry-including substrates and related stage | Steven E. Steen, Anna W. Topol | 2011-01-25 |
| 7723851 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias | Mark Todhunter Robson | 2010-05-25 |
| 7704869 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias | Mark Todhunter Robson | 2010-04-27 |
| 7666723 | Methods of forming wiring to transistor and related transistor | David J. Frank, Steven E. Steen, Anna W. Topol | 2010-02-23 |
| 7528056 | Low-cost strained SOI substrate for high-performance CMOS technology | Meikei Ieong, Leathen Shi, Anna W. Topol, James Vichiconti, Albert M. Young | 2009-05-05 |
| 7494915 | Back end interconnect with a shaped interface | Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor +8 more | 2009-02-24 |
| 7488630 | Method for preparing 2-dimensional semiconductor devices for integration in a third dimension | David J. Frank, Leathen Shi, Steven E. Steen, Anna W. Topol | 2009-02-10 |
| 7241681 | Bilayered metal hardmasks for use in dual damascene etch schemes | Kaushik A. Kumar, Lawrence A. Clevenger, Timothy J. Dalton, Andy Cowley, Erdem Kaltalioglu +5 more | 2007-07-10 |
| 7241696 | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | Larry Clevenger, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik A. Kumar +5 more | 2007-07-10 |
| 7125792 | Dual damascene structure and method | Kaushik A. Kumar, Timothy J. Dalton, Larry Clevenger, Andy Cowley, Erdem Kaltalioglu +1 more | 2006-10-24 |
| 7122462 | Back end interconnect with a shaped interface | Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor +8 more | 2006-10-17 |
| 7091612 | Dual damascene structure and method | Kaushik A. Kumar, Timothy J. Dalton, Larry Clevenger, Andy Cowley, Mark Hoinkis +5 more | 2006-08-15 |
| 7052621 | Bilayered metal hardmasks for use in Dual Damascene etch schemes | Kaushik A. Kumar, Lawrence A. Clevenger, Timothy J. Dalton, Andy Cowley, Erdem Kaltalioglu +5 more | 2006-05-30 |