CP

Christopher M. Prindle

Globalfoundries: 18 patents #182 of 4,424Top 5%
FS Freeescale Semiconductor: 1 patents #2,021 of 3,767Top 55%
IBM: 1 patents #44,794 of 70,183Top 65%
Overall (All Time): #221,987 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10734525 Gate-all-around transistor with spacer support and methods of forming same Ruilong Xie, Julien Frougier, Nigel G. Cave 2020-08-04
10699965 Removal of epitaxy defects in transistors Andrew M. Greene, Ruilong Xie, Pietro Montanini 2020-06-30
10388770 Gate and source/drain contact structures positioned above an active region of a transistor device Ruilong Xie, Chanro Park 2019-08-20
10388747 Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure Ruilong Xie, Emilie Bourjot, Laertis Economikos 2019-08-20
10290738 Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device Ruilong Xie, Kwan-Yong Lim 2019-05-14
10170544 Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region Ruilong Xie, Min Gyu Sung, Tek Po Rinus Lee 2019-01-01
10068978 Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression Kwan-Yong Lim 2018-09-04
9876077 Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices Ruilong Xie, Min Gyu Sung, Tek Po Rinus Lee 2018-01-23
9806078 FinFET spacer formation on gate sidewalls, between the channel and source/drain regions Ruilong Xie, Tenko Yamashita, Balasubramanian Pranatharthiharan, Pietro Montanini, Soon-Cheon Seo 2017-10-31
9685384 Devices and methods of forming epi for aggressive gate pitch Ruilong Xie, Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Pietro Montanini, Shogo Mochizuki 2017-06-20
9640533 Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression Kwan-Yong Lim 2017-05-02
9496354 Semiconductor devices with dummy gate structures partially on isolation regions Ruilong Xie, Xiuyu Cai, Ajey Poovannummoottil Jacob, Andreas Knorr 2016-11-15
9236452 Raised source/drain EPI with suppressed lateral EPI overgrowth Kwan-Yong Lim, Jody A. Fronheiser 2016-01-12
9230802 Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication Neeraj Tripathi 2016-01-05
9184263 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices Xiuyu Cai, Ajey Poovannummoottil Jacob, Daniel T. Pham, Mark V. Raymond, Catherine B. Labelle +2 more 2015-11-10
9147748 Methods of forming replacement spacer structures on semiconductor devices Ruilong Xie, Xiuyu Cai, Ajey Poovannummoottil Jacob, Andreas Knorr 2015-09-29
8748302 Replacement gate approach for high-k metal gate stacks by using a multi-layer contact level Johannes Groschopf, Andreas Ott 2014-06-10
8735236 High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology Klaus Hempel, Rolf Stephan 2014-05-27
7601641 Two step optical planarizing layer etch Erik Geiss, Sven Beyer 2009-10-13
6924232 Semiconductor process and composition for forming a barrier material overlying copper Varughese Mathew, Sam S. Garcia 2005-08-02