Issued Patents All Time
Showing 201–225 of 394 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10290614 | Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits | Han Wui Then, Robert S. Chau, Valluri Rao, Niloy Mukherjee, Marko Radosavljevic +2 more | 2019-05-14 |
| 10263079 | Apparatus and methods for forming a modulation doped non-planar transistor | Mantu K. Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros | 2019-04-16 |
| 10263074 | High voltage field effect transistors | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros +3 more | 2019-04-16 |
| 10249490 | Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy | Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz +7 more | 2019-04-02 |
| 10236369 | Techniques for forming non-planar germanium quantum well devices | Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic +4 more | 2019-03-19 |
| 10224399 | Strain compensation in transistors | Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Jack T. Kavalieros | 2019-03-05 |
| 10217673 | Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith | Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung +1 more | 2019-02-26 |
| 10201081 | Electronic fabric with incorporated chip and interconnect | Christopher J. Jezewski, Brian S. Doyle | 2019-02-05 |
| 10186580 | Semiconductor device having germanium active layer with underlying diffusion barrier layer | Willy Rachmady, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Harold W. Kennel | 2019-01-22 |
| 10186581 | Group III-N nanowire transistors | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros +3 more | 2019-01-22 |
| 10177249 | Techniques for forming contacts to quantum well transistors | Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady +2 more | 2019-01-08 |
| 10103263 | Strained channel region transistors employing source and drain stressors and systems including the same | Van H. Le, Harold W. Kennel, Willy Rachmady, Jack T. Kavalieros, Niloy Mukherjee | 2018-10-16 |
| 10096709 | Aspect ratio trapping (ART) for fabricating vertical semiconductor devices | Van H. Le, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady +4 more | 2018-10-09 |
| 10096682 | III-N devices in Si trenches | Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Seung Hoon Sung, Marko Radosavljevic +3 more | 2018-10-09 |
| 10090461 | Oxide-based three-terminal resistive switching logic devices | Elijah V. Karpov, Prashant Majhi, Brian S. Doyle, Niloy Mukherjee, Uday Shah +1 more | 2018-10-02 |
| 10090405 | Semiconductor device having group III-V material active region and graded gate dielectric | Gilbert Dewey, Marko Radosavljevic, Matthew V. Metz | 2018-10-02 |
| 10084058 | Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains | Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Marko Radosavljevic, Gilbert Dewey +2 more | 2018-09-25 |
| 10074718 | Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack | Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee | 2018-09-11 |
| 10050015 | Multi-device flexible electronics system on a chip (SOC) process integration | Sansaptak Dasgupta, Niloy Mukherjee, Brian S. Doyle, Marko Radosavljevic, Han Wui Then | 2018-08-14 |
| 10038054 | Variable gate width for gate all-around transistors | Willy Rachmady, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Seung Hoon Sung | 2018-07-31 |
| 10032911 | Wide band gap transistor on non-native semiconductor substrate | Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung +2 more | 2018-07-24 |
| 10026845 | Deep gate-all-around semiconductor device having germanium or group III-V active layer | Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros +5 more | 2018-07-17 |
| 10020371 | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors | Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Gilbert Dewey, Niloy Mukherjee +3 more | 2018-07-10 |
| 10008565 | Semiconductor devices with germanium-rich active layers and doped transition layers | Willy Rachmady, Van H. Le, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich | 2018-06-26 |
| 9972686 | Germanium tin channel transistors | Van H. Le, Willy Rachmady, Roza Kotlyar, Marko Radosavljevic, Han Wui Then +4 more | 2018-05-15 |