Issued Patents All Time
Showing 51–75 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10296457 | Reducing conflicts in direct mapped caches | Ruchira Sasanka | 2019-05-21 |
| 10275001 | Thermal throttling of electronic devices | Timothy Y. Kam, Sandeep Ahuja, Avinash Sodani, Jinho Suh, Meenakshisundaram R. Chinthamani | 2019-04-30 |
| 10241912 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman +5 more | 2019-03-26 |
| 10198354 | Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory | Wei-Pin Chen, Jing Ling, Daniel W. Liu | 2019-02-05 |
| 10102126 | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes | Raj K. Ramanujan, Glenn J. Hinton | 2018-10-16 |
| 9910728 | Method and apparatus for partial cache line sparing | Debaleena Das, Brian S. Morris | 2018-03-06 |
| 9691505 | Dynamic application of error correction code (ECC) based on error type | Debaleena Das | 2017-06-27 |
| 9646910 | Integrated heat spreader that maximizes heat transfer from a multi-chip package | Sandeep Ahuja, Eric W. Buddrius, Roger D. Flynn | 2017-05-09 |
| 9613722 | Method and apparatus for reverse memory sparing | George H. Huang, Debaleena Das, Brian S. Morris | 2017-04-04 |
| 9600416 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman +5 more | 2017-03-21 |
| 9378142 | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes | Raj K. Ramanujan, Glenn J. Hinton | 2016-06-28 |
| 9257364 | Integrated heat spreader that maximizes heat transfer from a multi-chip package | Sandeep Ahuja, Eric W. Buddrius, Roger D. Flynn | 2016-02-09 |
| 9195551 | Enhanced storage of metadata utilizing improved error detection and correction in computer memory | Debaleena Das, C. Scott Huddleston | 2015-11-24 |
| 9043674 | Error detection and correction apparatus and method | Wei Wu, Shih-Lien Linus Lu, Henry Stracovsky | 2015-05-26 |
| 8964580 | Device topology and capability discovery and reporting techniques | Adrian Muntianu, Cameron Buschardt, Yi-Shing Chu (Michael) Chu | 2015-02-24 |
| 8612832 | Mechanisms and techniques for providing cache tags in dynamic random access memory | Darrell S. McGinnis, C. Scott Huddleston, Meenakshisundaram R. Chinthamani | 2013-12-17 |
| 8438452 | Poison bit error checking code scheme | Scott Alan Huddleston, Dennis W. Brzezinski | 2013-05-07 |
| 8239737 | Data line storage and transmission utilizing both error correcting code and synchronization information | C. Scott Huddleston | 2012-08-07 |
| 8122265 | Power management using adaptive thermal throttling | Sivakumar Radhakrishnan, Suneeta Sah, William Harry Nale, Rami Naqib, Howard S. David | 2012-02-21 |
| 8069327 | Commands scheduled for frequency mismatch bubbles | Ramesh Subashchandrabose, Anupam Mohanty | 2011-11-29 |
| 8060692 | Memory controller using time-staggered lockstep sub-channels with buffered memory | Bruce A. Christenson | 2011-11-15 |
| 8041898 | Method, system and apparatus for reducing memory traffic in a distributed memory system | Adrian C. Moga, Malcolm Mandviwalla | 2011-10-18 |
| 7941618 | Fully buffered DIMM read data substitution for write acknowledgement | James W. Alexander, Bruce A. Christenson, Kai Cheng | 2011-05-10 |
| 7734980 | Mitigating silent data corruption in a buffered memory module architecture | James W. Alexander, Suresh Chittor, Dennis W. Brzezinski, Kai Cheng | 2010-06-08 |
| 7644347 | Silent data corruption mitigation using error correction code with embedded signaling fault detection | James W. Alexander, Suresh Chittor, Dennis W. Brzezinski, Kai Cheng, Henk G. Neefs | 2010-01-05 |