Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12197357 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2025-01-14 |
| 12189550 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2025-01-07 |
| 11741030 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2023-08-29 |
| 11269793 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2022-03-08 |
| 10969997 | Memory controller that filters a count of row activate commands collectively sent to a set of memory banks | — | 2021-04-06 |
| 10825534 | Per row activation count values embedded in storage cell array storage cells | — | 2020-11-03 |
| 10248591 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2019-04-02 |
| 9626321 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2017-04-18 |
| 8272781 | Dynamic power control of a memory device thermal sensor | — | 2012-09-25 |
| 8122265 | Power management using adaptive thermal throttling | Sivakumar Radhakrishnan, Suneeta Sah, Rami Naqib, Howard S. David, Rajat Agarwal | 2012-02-21 |
| 5987581 | Configurable address line inverter for remapping memory | — | 1999-11-16 |
| 5793385 | Address translator for a shared memory computing system | — | 1998-08-11 |
| 5276833 | Data cache management system with test mode using index registers and CAS disable and posted write disable | Stuart T. Auvinen | 1994-01-04 |