Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5802548 | Software programmable edge delay for SRAM write enable signals on dual purpose cache controllers | — | 1998-09-01 |
| 5490257 | RAM based FIFO memory half-full detection apparatus and method | Barry A. Hoberman, Patrick Wang, David T. Wang | 1996-02-06 |
| 5276833 | Data cache management system with test mode using index registers and CAS disable and posted write disable | William Harry Nale | 1994-01-04 |
| 5271098 | Method and apparatus for use of expanded memory system (EMS) to access cartridge memory | Rashid N. Khan, Funkai Liu | 1993-12-14 |
| 5210856 | Non-aligned DRAM state machine for page-mode DRAM control | Richard Sowell | 1993-05-11 |
| 4975879 | Biasing scheme for FIFO memories | — | 1990-12-04 |
| 4954987 | Interleaved sensing system for FIFO and burst-mode memories | Barry A. Hoberman | 1990-09-04 |
| 4802122 | Fast flush for a first-in first-out memory | Barry A. Hoberman | 1989-01-31 |