Issued Patents All Time
Showing 25 most recent of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12205669 | Memory buffer with data scrambling and error correction | Christopher Haywood | 2025-01-21 |
| 12204758 | Near-memory compute module | Nirmal Saxena | 2025-01-21 |
| 11854658 | Memory buffer with data scrambling and error correction | Christopher Haywood | 2023-12-26 |
| 11733870 | Near-memory compute module | Nirmal Saxena | 2023-08-22 |
| 11496527 | Distributed session function architecture system and methods | — | 2022-11-08 |
| 11282552 | Memory buffer with data scrambling and error correction | Christopher Haywood | 2022-03-22 |
| 10983700 | Buffering device with status communication method for memory controller | — | 2021-04-20 |
| 10764361 | Distributed server architecture session count system and methods | — | 2020-09-01 |
| 10607669 | Memory buffer with data scrambling and error correction | Christopher Haywood | 2020-03-31 |
| 10606483 | Buffering device with status communication method for memory controller | — | 2020-03-31 |
| 10264077 | System and methods for employing non-related communication architecture for signaling in another communication architecture | Chris Aaker | 2019-04-16 |
| 10263379 | Large deflection canted coil springs, connectors, and related methods | — | 2019-04-16 |
| 10198187 | Buffering device with status communication method for memory controller | — | 2019-02-05 |
| 10185499 | Near-memory compute module | Nirmal Saxena | 2019-01-22 |
| 10013371 | Configurable memory circuit system and method | Suresh Rajan, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2018-07-03 |
| 9972369 | Memory buffer with data scrambling and error correction | Christopher Haywood | 2018-05-15 |
| 9727458 | Translating an address associated with a command communicated between a system and memory circuits | Suresh Rajan, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2017-08-08 |
| 9632929 | Translating an address associated with a command communicated between a system and memory circuits | Suresh Rajan, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2017-04-25 |
| 9542352 | System and method for reducing command scheduling constraints of memory circuits | Suresh Rajan, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2017-01-10 |
| 9542353 | System and method for reducing command scheduling constraints of memory circuits | Suresh Rajan, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2017-01-10 |
| 9507739 | Configurable memory circuit system and method | Suresh Rajan, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2016-11-29 |
| 9349433 | Hidden refresh of weak memory storage cells in semiconductor memory | — | 2016-05-24 |
| 9348539 | Memory centric computing | Nirmal Saxena, Christopher Haywood, Eric McDonald, Chao Xu | 2016-05-24 |
| 9317366 | Protocol checking logic circuit for memory system reliability | — | 2016-04-19 |
| 9250831 | Isolated shared memory architecture (iSMA) | Nirmal Saxena, Sreenivas Krishnan | 2016-02-02 |