Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12416093 | Electroless plating process | Chandrasekharan Nair, Darko Grujicic, Rengarajan Shanmugam, Srinivasan Raman, Roy Dittler +3 more | 2025-09-16 |
| 12349282 | Capacitors in through glass vias | Benjamin Duong, Aleksandar Aleksov, Helme A. CASTRO DE LA TORRE, Kristof Darmawikarta, Darko Grujicic +5 more | 2025-07-01 |
| 12159825 | Dielectric-to-metal adhesion promotion material | Rahul N. Manepalli, Suddhasattwa Nad, Darko Grujicic | 2024-12-03 |
| 12057252 | Electronic substrates having embedded inductors | Benjamin Duong, Michael Garelick, Darko Grujicic, Tarek A. Ibrahim, Brandon C. Marin +1 more | 2024-08-06 |
| 12033930 | Selectively roughened copper architectures for low insertion loss conductive features | Jieying Kong, Yiyang Zhou, Suddhasattwa Nad, Jeremy Ecton, Hongxia Feng +9 more | 2024-07-09 |
| 11694898 | Hybrid fine line spacing architecture for bump pitch scaling | Suddhasattwa Nad, Jeremy Ecton, Bai Nie, Rahul N. Manepalli | 2023-07-04 |
| 11501967 | Selective metal deposition by patterning direct electroless metal plating | Suddhasattwa Nad, Roy Dittler, Darko Grujicic, Rahul N. Manepalli | 2022-11-15 |
| 11445616 | Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures | Suddhasattwa Nad, Rahul N. Manepalli | 2022-09-13 |
| 11291122 | Apparatus with a substrate provided with plasma treatment | Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian BAYRAKTAROGLU, Roy Dittler +4 more | 2022-03-29 |
| 11177232 | Circuit device with monolayer bonding between surface structures | Suddhasattwa Nad, Rahul N. Manepalli | 2021-11-16 |
| 11177234 | Package architecture with improved via drill process and method for forming such package | Suddhasattwa Nad, Rahul N. Manepalli | 2021-11-16 |
| 10658281 | Integrated circuit substrate and method of making | Rahul N. Manepalli, Kousik Ganesan, Srinivas V. Pietambaram | 2020-05-19 |