Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Marcel Wall — 13 Patents

Intel: 13 patents #3,167 of 30,777Top 15%
Phoenix, AZ: #475 of 6,660 inventorsTop 8%
Arizona: #2,773 of 32,909 inventorsTop 9%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Marcel Wall has been granted 13 US patents while listed as an inventor at Intel. The first was granted in 2020 and the most recent in November 2025. Marcel Wall ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Marcel Wall in Phoenix, AZ, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12476175 Glass substrates having transverse capacitors for use with semiconductor packages and related methods Benjamin Duong, Srinivas V. Pietambaram, Aleksandar Aleksov, Helme Castro De La Torre, Kristof Darmawikarta +5 more 2025-11-18
12416093 Electroless plating process Chandrasekharan Nair, Darko Grujicic, Rengarajan Shanmugam, Srinivasan Raman, Roy Dittler +3 more 2025-09-16
12349282 Capacitors in through glass vias Benjamin Duong, Aleksandar Aleksov, Helme A. CASTRO DE LA TORRE, Kristof Darmawikarta, Darko Grujicic +5 more 2025-07-01
12159825 Dielectric-to-metal adhesion promotion material Rahul N. Manepalli, Suddhasattwa Nad, Darko Grujicic 2024-12-03 $28,395,000
12057252 Electronic substrates having embedded inductors Benjamin Duong, Michael Garelick, Darko Grujicic, Tarek A. Ibrahim, Brandon C. Marin +1 more 2024-08-06 $17,070,000
12033930 Selectively roughened copper architectures for low insertion loss conductive features Jieying Kong, Yiyang Zhou, Suddhasattwa Nad, Jeremy Ecton, Hongxia Feng +9 more 2024-07-09 $24,938,000
11694898 Hybrid fine line spacing architecture for bump pitch scaling Suddhasattwa Nad, Jeremy Ecton, Bai Nie, Rahul N. Manepalli 2023-07-04
11501967 Selective metal deposition by patterning direct electroless metal plating Suddhasattwa Nad, Roy Dittler, Darko Grujicic, Rahul N. Manepalli 2022-11-15 $16,955,000
11445616 Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures Suddhasattwa Nad, Rahul N. Manepalli 2022-09-13 $14,653,000
11291122 Apparatus with a substrate provided with plasma treatment Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian BAYRAKTAROGLU, Roy Dittler +4 more 2022-03-29 $28,068,000
11177232 Circuit device with monolayer bonding between surface structures Suddhasattwa Nad, Rahul N. Manepalli 2021-11-16 $23,453,000
11177234 Package architecture with improved via drill process and method for forming such package Suddhasattwa Nad, Rahul N. Manepalli 2021-11-16 $23,453,000
10658281 Integrated circuit substrate and method of making Rahul N. Manepalli, Kousik Ganesan, Srinivas V. Pietambaram 2020-05-19 $31,576,000