Issued Patents All Time
Showing 201–225 of 396 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10818799 | Vertical transistor devices and techniques | Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Willy Rachmady | 2020-10-27 |
| 10811461 | Access transmission gate | Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le | 2020-10-20 |
| 10797150 | Differential work function between gate stack metals to reduce parasitic capacitance | Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Nadia M. Rahhal-Orabi +3 more | 2020-10-06 |
| 10784170 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Willy Rachmady +4 more | 2020-09-22 |
| 10770593 | Beaded fin transistor | Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Anand S. Murthy +1 more | 2020-09-08 |
| 10756198 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Niloy Mukherjee, Matthew V. Metz, Jack T. Kavalieros, Nancy Zelick, Robert S. Chau | 2020-08-25 |
| 10749032 | Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers | Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Willy Rachmady +2 more | 2020-08-18 |
| 10748900 | Fin-based III-V/SI or GE CMOS SAGE integration | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy +1 more | 2020-08-18 |
| 10734488 | Aluminum indium phosphide subfin germanium channel transistors | Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung +1 more | 2020-08-04 |
| 10734511 | High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer | Cheng-Ying Huang, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Benjamin Chu-Kung +1 more | 2020-08-04 |
| 10727138 | Integration of single crystalline transistors in back end of line (BEOL) | Van H. Le, Marko Radosavljevic, Benjamin Chu-Kung, Rafael Rios | 2020-07-28 |
| 10727339 | Selectively regrown top contact for vertical semiconductor devices | Benjamin Chu-Kung, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty +3 more | 2020-07-28 |
| 10707319 | Gate electrode having a capping layer | Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz | 2020-07-07 |
| 10693008 | Cladding layer epitaxy via template engineering for heterogeneous integration on silicon | Niloy Mukherjee, Marko Radosavljevic, Jack T. Kavalieros, Ravi Pillarisetty, Niti Goel +2 more | 2020-06-23 |
| 10665688 | Low Schottky barrier contact structure for Ge NMOS | Willy Rachmady, Matthew V. Metz, Benjamin Chu-Kung, Van H. Le, Ashish Agrawal +1 more | 2020-05-26 |
| 10659046 | Local cell-level power gating switch | Rafael Rios, Van H. Le, Jack T. Kavalieros | 2020-05-19 |
| 10651288 | Pseudomorphic InGaAs on GaAs for gate-all-around transistors | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Jack T. Kavalieros +2 more | 2020-05-12 |
| 10651313 | Reduced transistor resistance using doped layer | Cheng-Ying Huang, Matthew V. Metz, Willy Rachmady, Jack T. Kavalieros, Sean T. Ma | 2020-05-12 |
| 10644111 | Strained silicon layer with relaxed underlayer | Benjamin Chu-Kung, Van H. Le, Ashish Agrawal, Jack T. Kavalieros, Matthew V. Metz +2 more | 2020-05-05 |
| 10644123 | Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors | Van H. Le, Rafael Rios, Jack T. Kavalieros, Shriram Shivaraman | 2020-05-05 |
| 10644137 | III-V finfet transistor with V-groove S/D profile for improved access resistance | Willy Rachmady, Matthew V. Metz, Sean T. Ma, Chandra S. Mohapatra, Sanaz K. Gardner +3 more | 2020-05-05 |
| 10644140 | Integrated circuit die having back-end-of-line transistors | Van H. Le, Marko Radosavljevic, Rafael Rios, Jack T. Kavalieros | 2020-05-05 |
| 10636912 | FINFET transistor having a tapered subfin structure | Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros, Chandra S. Mohapatra, Sean T. Ma +2 more | 2020-04-28 |
| 10586848 | Apparatus and methods to create an active channel having indium rich side and bottom surfaces | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Matthew V. Metz, Willy Rachmady +2 more | 2020-03-10 |
| 10580865 | Transistor with a sub-fin dielectric region under a gate | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Nadia M. Rahhal-Orabi, Jack T. Kavalieros +2 more | 2020-03-03 |