Issued Patents All Time
Showing 26–50 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489063 | Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication | Asit K. Mishra, Deborah T. Marr | 2019-11-26 |
| 10452403 | Mechanism for instruction set based thread execution on a plurality of instruction sequencers | Hong Wang, John Shen, Richard Hankins, Gautham Chinya, Bryant Bigbee +9 more | 2019-10-22 |
| 10445245 | Method, system, and apparatus for page sizing extension | Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa | 2019-10-15 |
| 10445244 | Method, system, and apparatus for page sizing extension | Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa | 2019-10-15 |
| 10423411 | Data element comparison processors, methods, systems, and instructions | Asit K. Mishra, Jonathan Pearce, Deborah T. Marr, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more | 2019-09-24 |
| 10282296 | Zeroing a cache line | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Stephen H. Gunther, Buford M. Guy +5 more | 2019-05-07 |
| 10275243 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Asit K. Mishra, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. | 2019-04-30 |
| 10261904 | Memory sequencing with coherent and non-coherent sub-systems | Chunhui Zhang, George Z. Chrysos, Ramacharan Sundararaman, Chung-Lun Chan, Federico Ardanaz | 2019-04-16 |
| 10234930 | Performing power management in a multicore processor | Victor W. Lee, Daehyun Kim, Yuxin Bai, Sheng Li, Naveen Mellempudi +1 more | 2019-03-19 |
| 10146535 | Systems, apparatuses, and methods for chained fused multiply add | Jesus Corbal, Robert Valentine, Roman S. Dubtsov, Nikita A. Shustrov, Mark J. Charney +4 more | 2018-12-04 |
| 9990206 | Mechanism for instruction set based thread execution of a plurality of instruction sequencers | Hong Wang, John Shen, Richard Hankins, Gautham Chinya, Bryant Bigbee +9 more | 2018-06-05 |
| 9977674 | Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction | Jeffrey P. Rupley, II, Edward A. Brekelbaum, Bryan Black | 2018-05-22 |
| 9934155 | Method, system, and apparatus for page sizing extension | Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa | 2018-04-03 |
| 9934032 | Processors, methods, and systems to implement partial register accesses with masked full register accesses | Seyed Yahya Sotoudeh, Buford M. Guy | 2018-04-03 |
| 9898286 | Packed finite impulse response (FIR) filter processors, methods, systems, and instructions | Edwin Van Dalen, Martinus Cornelis Wezelenburg, Steven Roos, Moshe Maor | 2018-02-20 |
| 9875213 | Methods, apparatus, instructions and logic to provide vector packed histogram functionality | Galina Ryvchin, Michael Behar | 2018-01-23 |
| 9875185 | Memory sequencing with coherent and non-coherent sub-systems | Chunhui Zhang, George Z. Chrysos, Ramacharan Sundararaman, Chung-Lun Chan, Federico Ardanaz | 2018-01-23 |
| 9785436 | Apparatus and method for efficient gather and scatter operations | Dennis R. Bradford, George Z. Chrysos, Andrew T. Forsyth, Michael D. Upton, Lisa K. Wu | 2017-10-10 |
| 9513917 | Vector friendly instruction format and execution thereof | Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more | 2016-12-06 |
| 9477467 | Processors, methods, and systems to implement partial register accesses with masked full register accesses | Seyed Yahya Sotoudeh, Buford M. Guy | 2016-10-25 |
| 9465670 | Generational thread scheduler using reservations for fair scheduling | Michael D. Upton, George Z. Chrysos, Chunhui Zhang, Mohammed L. Al-Aqrabawi | 2016-10-11 |
| 9442721 | Method and system to provide user-level multithreading | Hong Wang, John Shen, Perry Wang, Jamison D. Colins, James P. Held +3 more | 2016-09-13 |
| 9367314 | Converting conditional short forward branches to computationally equivalent predicated instructions | Martin G. Dixon, Yazmin A. Santiago, Mishali Naik | 2016-06-14 |
| 9189230 | Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution | Hong Wang, John Shen, Perry Wang, Jamison D. Collins, James P. Held +3 more | 2015-11-17 |
| 9170955 | Providing extended cache replacement state information | Andrew T. Forsyth, Ramacharan Sundararaman, Eric Sprangle, John Cruz Mejia, Douglas M. Carmean +1 more | 2015-10-27 |