Issued Patents All Time
Showing 76–100 of 180 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10586856 | Nanosheet FET device with epitaxial nucleation | Nicolas Loubet, Julien Frougier, Wenyu Xu | 2020-03-10 |
| 10586875 | Gate-all-around transistor based non-volatile memory devices | Zheng Xu, Dexin Kong, Qianwen Chen | 2020-03-10 |
| 10586737 | Method and structure for forming vertical transistors with shared gates and separate gates | Kangguo Cheng, Juntao Li, Peng Xu | 2020-03-10 |
| 10573566 | Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels | Kangguo Cheng, Peng Xu, Jie Yang | 2020-02-25 |
| 10566445 | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates | Kangguo Cheng, Nicolas Loubet, Xin Miao, Wenyu Xu, Chen Zhang | 2020-02-18 |
| 10553445 | Stacked nanowires | Kangguo Cheng, Juntao Li, Xin Miao | 2020-02-04 |
| 10553682 | Vertical transistors with multiple gate lengths | Kangguo Cheng, Peng Xu, Zheng Xu | 2020-02-04 |
| 10546788 | Dual channel FinFETs having uniform fin heights | Kangguo Cheng, Peng Xu, Jie Yang | 2020-01-28 |
| 10541176 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Kangguo Cheng, Juntao Li, Peng Xu | 2020-01-21 |
| 10541128 | Method for making VFET devices with ILD protection | Kangguo Cheng, Juntao Li, Peng Xu | 2020-01-21 |
| 10535755 | Closely packed vertical transistors with reduced contact resistance | Kangguo Cheng, Juntao Li, Peng Xu | 2020-01-14 |
| 10516028 | Transistor with asymmetric spacers | Kangguo Cheng, Heng Wu, Peng Xu | 2019-12-24 |
| 10510885 | Transistor with asymmetric source/drain overlap | Kangguo Cheng, Peng Xu, Heng Wu | 2019-12-17 |
| 10504793 | Hybrid-channel nano-sheet FETs | Kangguo Cheng, Peng Xu, Wenyu Xu | 2019-12-10 |
| 10490546 | Forming on-chip metal-insulator-semiconductor capacitor | Kangguo Cheng, Peng Xu, Chen Zhang | 2019-11-26 |
| 10483382 | Tunnel transistor | Kangguo Cheng, Peng Xu, Heng Wu | 2019-11-19 |
| 10475905 | Techniques for vertical FET gate length control | Chi-Chun Liu, Chun Wing Yeung, Robin Hsin Kuo Chao, Kristin Schmidt, Yann Mignot | 2019-11-12 |
| 10461154 | Bottom isolation for nanosheet transistors on bulk substrate | Yi Song, Chi-Chun Liu, Shogo Mochizuki | 2019-10-29 |
| 10446647 | Approach to minimization of strain loss in strained fin field effect transistors | Kangguo Cheng, Juntao Li, Peng Xu | 2019-10-15 |
| 10438855 | Dual channel FinFETs having uniform fin heights | Kangguo Cheng, Peng Xu, Jie Yang | 2019-10-08 |
| 10426400 | Optimized individual sleep patterns | Mahmoud Amin, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga | 2019-10-01 |
| 10420502 | Optimized individual sleep patterns | Mahmoud Amin, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga | 2019-09-24 |
| 10403716 | Trench contact resistance reduction | Kangguo Cheng, Juntao Li, Peng Xu | 2019-09-03 |
| 10395988 | Vertical FET transistor with reduced source/drain contact resistance | Kangguo Cheng, Zheng Xu, Ruqiang Bao | 2019-08-27 |
| 10388571 | Fin type field effect transistors with different pitches and substantially uniform fin reveal | Kangguo Cheng, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan | 2019-08-20 |