Issued Patents All Time
Showing 251–275 of 323 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9985096 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Chun-Chen Yeh | 2018-05-29 |
| 9985021 | Shallow trench isolation recess process flow for vertical field effect transistor fabrication | Zhenxing Bi, Kangguo Cheng, Bruce Miao | 2018-05-29 |
| 9972700 | Vertical field effect transistors with bottom source/drain epitaxy | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-05-15 |
| 9966430 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-05-08 |
| 9960164 | Flipped vertical field-effect-transistor | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-05-01 |
| 9935101 | Vertical field effect transistor with uniform gate length | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-04-03 |
| 9911656 | Wimpy device by selective laser annealing | Kangguo Cheng, Nicolas Loubet, Alexander Reznicek | 2018-03-06 |
| 9911834 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Ramachandra Divakaruni, Juntao Li | 2018-03-06 |
| 9911592 | Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure | Bruce B. Doris, Michael A. Guillorn, Isaac Lauer | 2018-03-06 |
| 9905663 | Fabrication of a vertical fin field effect transistor with a reduced contact resistance | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-02-27 |
| 9899524 | Split fin field effect transistor enabling back bias on fin type field effect transistors | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-02-20 |
| 9899515 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-02-20 |
| 9881842 | Wimpy and nominal semiconductor device structures for vertical finFETs | Kisup Chung, Su Chen Fan, Catherine B. Labelle | 2018-01-30 |
| 9876097 | Selectively formed gate sidewall spacer | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-01-23 |
| 9865705 | Vertical field effect transistors with bottom source/drain epitaxy | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-01-09 |
| 9865587 | Method and structure for forming buried ESD with FinFETs | Kangguo Cheng, Nicolas Loubet, Alexander Reznicek | 2018-01-09 |
| 9859409 | Single-electron transistor with wrap-around gate | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-01-02 |
| 9859389 | Sidewall protective layer for contact formation | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-01-02 |
| 9859174 | Sidewall image transfer structures | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-01-02 |
| 9859166 | Vertical field effect transistor having U-shaped top spacer | Kangguo Cheng, Wenyu Xu, Chen Zhang | 2018-01-02 |
| 9853132 | Nanosheet MOSFET with full-height air-gap spacer | Kangguo Cheng, Bruce B. Doris, Michael A. Guillorn | 2017-12-26 |
| 9853054 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Kangguo Cheng, Juntao Li, Zuoguang Liu | 2017-12-26 |
| 9853028 | Vertical FET with reduced parasitic capacitance | Kangguo Cheng, Philip J. Oldiges, Wenyu Xu, Chen Zhang | 2017-12-26 |
| 9847388 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Chun-Chen Yeh | 2017-12-19 |
| 9842929 | Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate | Kangguo Cheng, Nicolas Loubet, Alexander Reznicek | 2017-12-12 |