Issued Patents All Time
Showing 26–50 of 462 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11646306 | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate | Julien Frougier, Andrew Gaul, Ruilong Xie | 2023-05-09 |
| 11621332 | Wraparound contact to a buried power rail | Ruilong Xie, Alexander Reznicek, Junli Wang | 2023-04-04 |
| 11615988 | FinFET devices | Kangguo Cheng, Theodorus E. Standaert, Junli Wang | 2023-03-28 |
| 11443982 | Formation of trench silicide source or drain contacts without gate damage | Andrew M. Greene, Ruilong Xie, Laertis Economikos, Chanro Park, Hui Zang | 2022-09-13 |
| 11404560 | Punch through stopper in bulk finFET device | Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2022-08-02 |
| 11387319 | Nanosheet transistor device with bottom isolation | Ruilong Xie, Andrew M. Greene, Pietro Montanini | 2022-07-12 |
| 11380589 | Selective removal of semiconductor fins | Kangguo Cheng, Ali Khakifirooz | 2022-07-05 |
| 11355401 | Field effect transistor | Effendi Leobandung, Junli Wang, Albert M. Chu | 2022-06-07 |
| 11349001 | Replacement gate cross-couple for static random-access memory scaling | Ruilong Xie, Carl Radens, Kangguo Cheng, Juntao Li | 2022-05-31 |
| 11348999 | Nanosheet semiconductor devices with sigma shaped inner spacer | Alexander Reznicek, Chun-Chen Yeh, Junli Wang | 2022-05-31 |
| 11349029 | Structure to enable titanium contact liner on pFET source/drain regions | Keith E. Fogel, Nicole S. Munro, Alexander Reznicek | 2022-05-31 |
| 11239343 | Vertical transistor including symmetrical source/drain extension junctions | Chun-Chen Yeh, Alexander Reznicek, Junli Wang | 2022-02-01 |
| 11239115 | Partial self-aligned contact for MOL | Ruilong Xie, Alexander Reznicek, Junli Wang | 2022-02-01 |
| 11227923 | Wrap around contact process margin improvement with early contact cut | Ruilong Xie, Andrew M. Greene, Alexander Reznicek, Yao Yao | 2022-01-18 |
| 11201242 | Structure to enable titanium contact liner on pFET source/drain regions | Keith E. Fogel, Nicole S. Munro, Alexander Reznicek | 2021-12-14 |
| 11189693 | Transistor having reduced contact resistance | Kangguo Cheng, Theodorus E. Standaert, Junli Wang | 2021-11-30 |
| 11183558 | Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions | Chun-Chen Yeh, Alexander Reznicek, Junli Wang | 2021-11-23 |
| 11152464 | Self-aligned isolation for nanosheet transistor | Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Robert R. Robison | 2021-10-19 |
| 11145551 | FinFET devices | Kangguo Cheng, Theodoras E. Standaert, Junli Wang | 2021-10-12 |
| 11139372 | Dual step etch-back inner spacer formation | Andrew M. Greene, Yao Yao, Ruilong Xie | 2021-10-05 |
| 11139385 | Interface-less contacts to source/drain regions and gate electrode over active portion of device | Junli Wang, Huiming Bu | 2021-10-05 |
| 11121032 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Kangguo Cheng, Theodorus E. Standaert, Junli Wang | 2021-09-14 |
| 11094803 | Nanosheet device with tall suspension and tight contacted gate poly-pitch | Ruilong Xie, Julien Frougier, Ardasheir Rahman, Alexander Reznicek | 2021-08-17 |
| 11088280 | Transistor and method of forming same | Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2021-08-10 |
| 11081568 | Protective bilayer inner spacer for nanosheet devices | Yao Yao, Ruilong Xie, Andrew M. Greene | 2021-08-03 |