Issued Patents All Time
Showing 51–75 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8741678 | Transparent conductive electrode stack containing carbon-containing material | James B. Hannon, Ning Li, Satoshi Oida, George S. Tulevski, Devendra K. Sadana | 2014-06-03 |
| 8492852 | Interface structure for channel mobility improvement in high-k metal gate stack | Dechao Guo, Philip J. Oldiges, Yanfeng Wang | 2013-07-23 |
| 8383483 | High performance CMOS circuits, and methods for fabricating same | John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Michael P. Chudzik, Bruce B. Doris +7 more | 2013-02-26 |
| 8158481 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-Yung Sung, Richard S. Wise +2 more | 2012-04-17 |
| 8138574 | PCM with poly-emitter BJT access devices | Chung H. Lam, Bipin Rajendran | 2012-03-20 |
| 7847356 | Metal gate high-K devices having a layer comprised of amorphous silicon | Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri | 2010-12-07 |
| 7833849 | Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode | Alessandro C. Callegari, Michael P. Chudzik, Bruce B. Doris, Young-Hee Kim, Vijay Narayanan +3 more | 2010-11-16 |
| 7790592 | Method to fabricate metal gate high-k devices | Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri | 2010-09-07 |
| 7671421 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-Yung Sung, Richard S. Wise +2 more | 2010-03-02 |
| 7598097 | Method of fabricating a magnetic shift register | Stuart Stephen Papworth Parkin | 2009-10-06 |
| 7498235 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates | Guy M. Cohen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi | 2009-03-03 |
| 7435652 | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET | Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang | 2008-10-14 |
| 7416905 | Method of fabricating a magnetic shift register | Stuart S.P. Parkin | 2008-08-26 |
| 7315065 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates | Guy M. Cohen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi | 2008-01-01 |
| 7138319 | Deep trench isolation of embedded DRAM for improved latch-up immunity | Kiang-Kai Han | 2006-11-21 |
| 7108797 | Method of fabricating a shiftable magnetic shift register | Stuart Stephen Papworth Parkin | 2006-09-19 |
| 7084460 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates | Guy M. Cohen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi | 2006-08-01 |
| 6955926 | Method of fabricating data tracks for use in a magnetic shift register memory device | Stuart Stephen Papworth Parkin | 2005-10-18 |
| 6914320 | Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof | Brett H. Engel, John A. Fitzsimmons, Terence L. Kane, Naftall E. Lustig, Ann McDonald +5 more | 2005-07-05 |
| 6887783 | Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof | Brett H. Engel, John A. Fitzsimmons, Terence L. Kane, Naftall E. Lustig, Ann McDonald +5 more | 2005-05-03 |
| 6885080 | Deep trench isolation of embedded DRAM for improved latch-up immunity | Liang Han | 2005-04-26 |
| 6878611 | Patterned strained silicon for high performance circuits | Devendra K. Sadana, Stephen W. Bedell, Kwang Su Choe, Keith E. Fogel | 2005-04-12 |
| 6812114 | Patterned SOI by formation and annihilation of buried oxide regions during processing | Devendra K. Sadana | 2004-11-02 |
| 6657261 | Ground-plane device with back oxide topography | Fariborz Assaderaghi, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi | 2003-12-02 |
| 6635517 | Use of disposable spacer to introduce gettering in SOI layer | Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta, Paul A. Ronsheim +1 more | 2003-10-21 |