Issued Patents All Time
Showing 251–275 of 283 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9093496 | Process for faciltiating fin isolation schemes | Ajey Poovannummoottil Jacob, Kangguo Cheng, Bruce B. Doris, Prasanna Khare, Ramachandra Divakaruni | 2015-07-28 |
| 9082788 | Method of making a semiconductor device including an all around gate | Prasanna Khare, Huiming Bu | 2015-07-14 |
| 9070709 | Method for producing a field effect transistor with implantation through the spacers | Nicolas Posseme, Laurent Grenouillet, Yannick Le Tiec, Maud Vinet | 2015-06-30 |
| 9018057 | Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer | Qing Liu | 2015-04-28 |
| 9012999 | Semiconductor device with an inclined source/drain and associated methods | Qing Liu, Prasanna Khare | 2015-04-21 |
| 9006816 | Memory device having multiple dielectric gate stacks and related methods | Prasanna Khare, Stephane Allegret-Maret, Qing Liu, Hemanth Jagannathan, Lisa F. Edge +2 more | 2015-04-14 |
| 9000491 | Layer formation with reduced channel loss | Qing Liu, Prasanna Khare | 2015-04-07 |
| 9000555 | Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods | Qing Liu, Prasanna Khare | 2015-04-07 |
| 8993418 | Shallow heavily doped semiconductor layer by cyclic selective epitaxial deposition process | Vincent Destefanis | 2015-03-31 |
| 8987082 | Method of making a semiconductor device using sacrificial fins | Prasanna Khare | 2015-03-24 |
| 8975168 | Method for the formation of fin structures for FinFET devices | Qing Liu | 2015-03-10 |
| 8962430 | Method for the formation of a protective dual liner for a shallow trench isolation structure | Qing Liu, Bruce B. Doris | 2015-02-24 |
| 8956942 | Method of forming a fully substrate-isolated FinFET transistor | Prasanna Khare | 2015-02-17 |
| 8952420 | Method to induce strain in 3-D microfabricated structures | Pierre Morin | 2015-02-10 |
| 8900973 | Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion | Nathaniel Berliner, Pranita Kulkarni, Kingsuk Maitra, Sanjay C. Mehta, Paul A. Ronsheim +2 more | 2014-12-02 |
| 8900978 | Methods for making a semiconductor device with shaped source and drain recesses and related devices | Douglas Charles LaTulipe, Alexander Reznicek | 2014-12-02 |
| 8877600 | Method for manufacturing a hybrid SOI/bulk semiconductor wafer | Claire Fenouillet-Beranger, Stephane Denorme, Qing Liu, Emmanuel Richard, Pierre Perreau | 2014-11-04 |
| 8860123 | Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods | Prasanna Khare, Stephane Allegret-Maret, Qing Liu, Hemanth Jagannathan, Lisa F. Edge +2 more | 2014-10-14 |
| 8828851 | Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering | Prasanna Khare, Qing Liu | 2014-09-09 |
| 8796147 | Layer formation with reduced channel loss | Qing Liu, Prasanna Khare | 2014-08-05 |
| 8759874 | FinFET device with isolated channel | Prasanna Khare | 2014-06-24 |
| 8703550 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Maud Vinet | 2014-04-22 |
| 8592290 | Cut-very-last dual-EPI flow | Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth +3 more | 2013-11-26 |
| 8569152 | Cut-very-last dual-epi flow | Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth +3 more | 2013-10-29 |
| 8546203 | Semiconductor structure having NFET extension last implants | Kangguo Cheng, Bruce B. Doris, Bala Haran, Pranita Kulkarni, Amlan Majumdar +1 more | 2013-10-01 |