Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11631609 | Method for manufacturing a microelectronic device | Heimanu Niebojewski, Francois Andrieu | 2023-04-18 |
| 10930562 | Internal via with improved contact for upper semi-conductor layer of a 3D circuit | Fabrice Nemouchi, Maud Vinet | 2021-02-23 |
| 10319628 | Integrated circuit having a plurality of active layers and method of fabricating the same | Fabien Deprat, Perrine Batude, Laurent Brunet, Maud Vinet | 2019-06-11 |
| 10199276 | Semiconductor and metal alloy interconnections for a 3D circuit | Fabrice Nemouchi | 2019-02-05 |
| 10121707 | Method of fabrication of a FET transistor having an overlapped gate | Philippe Coronel | 2018-11-06 |
| 10115637 | Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit | Benoit Mathieu, Philippe Coronel | 2018-10-30 |
| 10074802 | Device with transistors distributed over several superimposed levels integrating a resistive memory | Elisa VIANELLO | 2018-09-11 |
| 10062681 | SOI integrated circuit equipped with a device for protecting against electrostatic discharges | Yohann Solaro, Sorin Cristoloveanu, Pascal Fonteneau | 2018-08-28 |
| 9997395 | Fabrication method of a stack of electronic devices | Frederic Gaillard, Benoit Mathieu, Fabrice Nemouchi | 2018-06-12 |
| 9852950 | Superimposed transistors with auto-aligned active zone of the upper transistor | Philippe Coronel | 2017-12-26 |
| 9793162 | Method for producing interconnections for 3D integrated circuit | Philippe Coronel | 2017-10-17 |
| 9786658 | Fabrication method of a stack of electronic devices | Benoit Mathieu | 2017-10-10 |
| 9779982 | Fabrication method of a stack of electronic devices | Perrine Batude, Laurent Brunet, Frank Fournel | 2017-10-03 |
| 9761583 | Manufacturing of self aligned interconnection elements for 3D integrated circuits | Bernard Previtali, Olivier Rozeau | 2017-09-12 |
| 9666577 | On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges | Yohann Solaro, Sorin Cristoloveanu, Pascal Fonteneau | 2017-05-30 |
| 9653476 | On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges | Pascal Fonteneau | 2017-05-16 |
| 9646846 | Method for producing a multilevel microelectronic structure | Philippe Coronel | 2017-05-09 |
| 9502566 | Method for producing a field effect transistor including forming a gate after forming the source and drain | Perrine Batude | 2016-11-22 |
| 9391057 | Integrated circuit on SOI comprising a transistor protecting from electrostatic discharges | Pascal Fonteneau | 2016-07-12 |
| 9337302 | On-SOI integrated circuit comprising a subjacent protection transistor | Pascal Fonteneau | 2016-05-10 |
| 9275891 | Process for fabricating an integrated circuit having trench isolations with different depths | Stephane Denorme | 2016-03-01 |
| 9165908 | On-SOI integrated circuit comprising a triac for protection against electrostatic discharges | Pascal Fonteneau | 2015-10-20 |
| 9165943 | ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges | Pascal Fonteneau | 2015-10-20 |
| 9029955 | Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths | Pascal Fonteneau | 2015-05-12 |
| 8936993 | Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate | Stephane Denorme, Philippe Coronel | 2015-01-20 |