Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12154930 | Three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functions | Gilles Sicard, Didier Lattard | 2024-11-26 |
| 11888007 | Image sensor formed in sequential 3D technology | Lina Kadura, Francois Andrieu, Christophe Licitra | 2024-01-30 |
| 11658260 | Method of manufacturing an optoelectronic device comprising a plurality of diodes | Hubert Bono | 2023-05-23 |
| 11552125 | Method of manufacturing an optoelectronic device comprising a plurality of diodes and an electronic circuit for controlling these diodes | Hubert Bono | 2023-01-10 |
| 11139209 | 3D circuit provided with mesa isolation for the ground plane zone | Francois Andrieu | 2021-10-05 |
| 11011425 | Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer | Francois Andrieu, Maud Vinet | 2021-05-18 |
| 10651202 | 3D circuit transistors with flipped gate | Francois Andrieu, Maud Vinet | 2020-05-12 |
| 10586740 | Method for manufacturing pairs of CMOS transistors of the “fin-FET” type at low temperatures | Benoit Mathieu | 2020-03-10 |
| 10553702 | Transistor with controlled overlap of access regions | Nicolas Posseme | 2020-02-04 |
| 10497627 | Method of manufacturing a dopant transistor located vertically on the gate | Nicolas Posseme, Laurent Brunet | 2019-12-03 |
| 10319628 | Integrated circuit having a plurality of active layers and method of fabricating the same | Fabien Deprat, Laurent Brunet, Claire Fenouillet-Beranger, Maud Vinet | 2019-06-11 |
| 10170621 | Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor | Shay Reboh, Flavia PIEGAS LUCE | 2019-01-01 |
| 9966453 | Method for doping source and drain regions of a transistor by means of selective amorphisation | Shay Reboh, Frédéric Mazen, Benoit Sklenard | 2018-05-08 |
| 9779982 | Fabrication method of a stack of electronic devices | Laurent Brunet, Claire Fenouillet-Beranger, Frank Fournel | 2017-10-03 |
| 9761607 | Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate | Shay Reboh, Sylvain Maitrejean, Frédéric Mazen | 2017-09-12 |
| 9502566 | Method for producing a field effect transistor including forming a gate after forming the source and drain | Claire Fenouillet-Beranger | 2016-11-22 |
| 9379213 | Method for forming doped areas under transistor spacers | Jean-Michel Hartmann, Benoit Sklenard, Maud Vinet | 2016-06-28 |
| 9343375 | Method for manufacturing a transistor in which the strain applied to the channel is increased | Frédéric Mazen, Shay Reboh, Benoit Sklenard | 2016-05-17 |
| 9246006 | Recrystallization of source and drain blocks from above | Frédéric Mazen, Benoit Sklenard, Shay Reboh | 2016-01-26 |
| 9018078 | Method of making a 3D integrated circuit | Benoit Sklenard | 2015-04-28 |
| 8853785 | Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit | Emmanuel Augendre, Maud Vinet, Laurent Clavelier | 2014-10-07 |
| 8722471 | Method for forming a via contacting several levels of semiconductor layers | Yves Morand | 2014-05-13 |
| 8183630 | Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT | Laurent Clavelier, Marie-Anne Jaud, Olivier Thomas, Maud Vinet | 2012-05-22 |
| 8013399 | SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable | Olivier Thomas, Arnaud Pouydebasque, Maud Vinet | 2011-09-06 |