JH

Jean-Michel Hartmann

CEA: 20 patents #109 of 7,956Top 2%
CN CNRS: 2 patents #1,756 of 11,908Top 15%
SO Soitec: 1 patents #140 of 259Top 55%
SS Stmicroelectronics (Crolles 2) Sas: 1 patents #308 of 529Top 60%
SS Stmicroelectronics Sa: 1 patents #2,729 of 4,662Top 60%
UA Universite Grenoble Alpes: 1 patents #96 of 431Top 25%
Overall (All Time): #214,956 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDate
12417942 Process for hydrophilically bonding substrates Vincent Larrey, Francois Rieutord, Frank Fournel, Didier Landru, Oleg Kononchuk +1 more 2025-09-16
12327719 Semiconductor substrate polishing method Shay Reboh, Frédéric Mazen, Frederic Milesi 2025-06-10
12282192 Method for fabricating a photonic chip Leopold VIROT, Karim Hassan, Bertrand Szelag, Quentin Wilmart 2025-04-22
12166063 Optoelectronic device having an array of germanium-based diodes with low dark current Jean-Louis Ouvrier-Buffet, Abdelkader Aliane, Julie Widiez 2024-12-10
11688629 Low-temperature method for manufacturing a semiconductor-on-insulator substrate Shay Reboh 2023-06-27
11600740 Contacting area on germanium Willy Ludurczak, Abdelkader Aliane, Zouhir Mehrez, Philippe Rodriguez 2023-03-07
11515394 Method for the nanoscale etching of a germanium-tin alloy (GeSn) for a FET transistor Etienne Eustache, Bassem Salem, Franck BASSANI, Mohamed-Aymen Mahjoub 2022-11-29
11450776 Contacting area on germanium Willy Ludurczak, Philippe Rodriguez, Abdelkader Aliane, Zouhir Mehrez 2022-09-20
11380543 Method for fabricating a monocrystalline structure Pierre RAYNAL, Pascal Besson, Virginie Loup, Laurent Vallier 2022-07-05
11264425 Process for fabricating an array of germanium-based diodes with low dark current Jean-Louis Ouvrier-Buffet, Abdelkader Aliane, Julie Widiez 2022-03-01
11236417 Method for producing Ge-core based waveguides Mickael Brun, Jean-Marc Fedeli, Maryse Fournier 2022-02-01
11231550 Waveguide manufacturing process Corrado Sciancalepore, Houssein El Dirani 2022-01-25
10699902 Process for producing a strained layer based on germanium-tin Vincent Reboud, Alexei Tchelnokov, Vincent Calvo 2020-06-30
10354870 Method for determining preferential deposition parameters for a thin layer of III-V material Yann Bogumilowicz 2019-07-16
9460923 Method of forming a strained silicon layer Aomar Halimaoui 2016-10-04
9379213 Method for forming doped areas under transistor spacers Perrine Batude, Benoit Sklenard, Maud Vinet 2016-06-28
9246045 Method for fabricating a photodetector Yann Bogumilowicz, Jean-Marc Fedeli 2016-01-26
8486810 Method for fabricating a substrate provided with two active areas with different semiconductor materials 2013-07-16
8110460 Method for producing stacked and self-aligned components on a substrate Romain Wacquez, Philippe Coronel, Vincent Destefanis 2012-02-07
6946369 Method for forming, by CVD, nanostructures of semi-conductor material of homogenous and controlled size on dielectric material Frédéric Mazen, Thierry Baron, Marie-Noelle Semeria 2005-09-20