VL

Virginie Loup

CEA: 3 patents #1,381 of 7,956Top 20%
CN CNRS: 2 patents #1,756 of 11,908Top 15%
UA Universite Grenoble Alpes: 2 patents #31 of 431Top 8%
📍 Pessac, FR: #51 of 240 inventorsTop 25%
Overall (All Time): #1,399,798 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11756787 Process for the hetero-integration of a semiconductor material of interest on a silicon substrate Mickaël Martin, Thierry Baron 2023-09-12
11380543 Method for fabricating a monocrystalline structure Pierre RAYNAL, Pascal Besson, Jean-Michel Hartmann, Laurent Vallier 2022-07-05
9831095 Method for performing selective etching of a semiconductor material in solution Pascal Besson 2017-11-28