Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417919 | Method for producing a superconducting vanadium silicide on a silicon layer | Thierry Farjot, Frédéric Gustavo, François LEFLOCH, Tom Doekle Vethaak | 2025-09-16 |
| 12408405 | Device comprising spacers including a localised airgap and associated manufacturing methods | Cyrille Le Royer, Nicolas Posseme | 2025-09-02 |
| 12402542 | Josephson transistor | Frédéric Gustavo, François LEFLOCH, Tom Doekle Vethaak | 2025-08-26 |
| 11941485 | Method of making a quantum device | Nicolas Posseme, Louis HUTIN, Cyrille Le Royer, François LEFLOCH, Maud Vinet | 2024-03-26 |
| 11929290 | Method of manufacturing microelectronic components | Clemens Fitz, Nicolas Posseme | 2024-03-12 |
| 11698488 | Method for fabricating a heterostructure comprising active or passive elementary structure made of III-V material on the surface of a silicon-based substrate | Charles Baudot, Yann Bogumilowicz, Elodie Ghegin, Philippe Rodriguez | 2023-07-11 |
| 11631739 | Transistor having blocks of source and drain silicides near the channel | Antonio Lacerda Santos Neto, François LEFLOCH | 2023-04-18 |
| 11515148 | Method for producing at least one device in compressive strained semiconductor | Loic Gaben, Cyrille Le Royer, Nicolas Posseme, Shay Reboh | 2022-11-29 |
| 11387147 | Method for producing a component by filling a cavity within an electrical isolation area with carbon-based material | Nicolas Posseme, Cyrille Le Royer | 2022-07-12 |
| 11362181 | Method for manufacturing an electronic component having multiple quantum dots | Nicolas Posseme, Louis HUTIN, Cyrille Le Royer | 2022-06-14 |
| 11217446 | Method for fabricating an integrated circuit including a NMOS transistor and a PMOS transistor | Nicolas Posseme, Loic Gaben, Cyrille Le Royer, Shay Reboh | 2022-01-04 |
| 11075501 | Process for producing a component comprising III-V materials and contacts compatible with silicon process flows | Elodie Ghegin, Christophe Jany, Philippe Rodriguez, Bertrand Szelag | 2021-07-27 |
| 10930562 | Internal via with improved contact for upper semi-conductor layer of a 3D circuit | Claire Fenouillet-Beranger, Maud Vinet | 2021-02-23 |
| 10388653 | Formation of Ohmic contacts for a device provided with a region made of III-V material and a region made of another semiconductor material | Philippe Rodriguez, Elodie Ghegin | 2019-08-20 |
| 10361087 | Process for producing an intermetallic contact based on Ni on InxGa1-xAs | Philippe Rodriguez, Seifeddine Zhiou, Patrice Gergaud | 2019-07-23 |
| 10340361 | Forming of a MOS transistor based on a two-dimensional semiconductor material | Yves Morand | 2019-07-02 |
| 10199276 | Semiconductor and metal alloy interconnections for a 3D circuit | Claire Fenouillet-Beranger | 2019-02-05 |
| 9997395 | Fabrication method of a stack of electronic devices | Claire Fenouillet-Beranger, Frederic Gaillard, Benoit Mathieu | 2018-06-12 |
| 9911827 | SBFET transistor and corresponding fabrication process | Louis HUTIN, Julien BORREL, Yves Morand | 2018-03-06 |
| 9831319 | Transistor with MIS connections and fabricating process | Julien BORREL, Louis HUTIN, Yves Morand, Heimanu Niebojewski | 2017-11-28 |
| 9548210 | Fabrication method of a transistor with improved field effect | Emilie Bourjot | 2017-01-17 |
| 9379024 | Method for manufacturing a microelectronic device including depositing identical or different metallic layers on the same wafer | Claire Fournier, Frederic Gaillard | 2016-06-28 |
| 9269570 | Contact on a heterogeneous semiconductor substrate | Yves Morand, Charles Baudot | 2016-02-23 |
| 9093552 | Manufacturing method for a device with transistors strained by silicidation of source and drain zones | Patrice Gergaud, Thierry Poiroux, Bernard Previtali | 2015-07-28 |
| 8822332 | Method for forming gate, source, and drain contacts on a MOS transistor | Heimanu Niebojewski, Yves Morand, Cyrille Le Royer | 2014-09-02 |