Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10914703 | Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET | Olivier Rozeau, Marie-Anne Jaud, Joris LACORD, Sébastien Martinie | 2021-02-09 |
| 9235668 | Computer implemented method for calculating a charge density at a gate interface of a double gate transistor | Marie-Anne Jaud, Sébastien Martinie, Olivier Rozeau | 2016-01-12 |
| 9093552 | Manufacturing method for a device with transistors strained by silicidation of source and drain zones | Fabrice Nemouchi, Patrice Gergaud, Bernard Previtali | 2015-07-28 |
| 8877622 | Process for producing an integrated circuit | Sebastien Barnola, Yves Morand | 2014-11-04 |
| 8866225 | Field effect transistor with alternate electrical contacts | Frédéric Mayer, Laurent Clavelier, Gérard Billiot | 2014-10-21 |
| 8664104 | Method of producing a device with transistors strained by means of an external layer | Fabrice Nemouchi, Patrice Gergaud, Bernard Previtali | 2014-03-04 |
| 8656584 | Method of fabricating an electromechanical component using graphene | Jean-Christophe P. Gabriel, Philippe Andreucci, Thomas Ernst | 2014-02-25 |
| 8598038 | Process for producing two interleaved patterns on a substrate | Yves Morand | 2013-12-03 |
| 8530292 | Method for manufacturing a strained channel MOS transistor | Yves Morand, Jean-Charles Barbe | 2013-09-10 |
| 8399316 | Method for making asymmetric double-gate transistors | Maud Vinet, Olivier Thomas, Olivier Rozeau | 2013-03-19 |
| 8349667 | Method for stabilizing germanium nanowires obtained by condensation | Emeline SARACCO, Jean-Francois Damlencourt | 2013-01-08 |
| 8324057 | Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate | Maud Vinet, Olivier Thomas, Olivier Rozeau | 2012-12-04 |
| 8232168 | Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate | Maud Vinet, Olivier Thomas, Olivier Rozeau | 2012-07-31 |
| 8105906 | Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate | Maud Vinet, Olivier Thomas, Olivier Rozeau | 2012-01-31 |
| 8021934 | Method for making a transistor with metallic source and drain | Maud Vinet, Bernard Previtali | 2011-09-20 |
| 8021986 | Method for producing a transistor with metallic source and drain | Bernard Previtali, Maud Vinet | 2011-09-20 |
| 7968945 | Microelectronic device provided with transistors coated with a piezoelectric layer | Jerome Lolivier, Maud Vinet | 2011-06-28 |
| 7829916 | Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor | Yves Morand, Maud Vinet | 2010-11-09 |
| 7473588 | Method for insulating patterns formed in a thin film of oxidizable semi-conducting material | Maud Vinet, Jean-Charles Barbe, Bernard Previtali | 2009-01-06 |
| 7361592 | Method for producing a component comprising at least one germanium-based element and component obtained by such a method | Yves Morand, Maud Vinet | 2008-04-22 |
| 6779161 | Process and device for evaluating a CMOS logical cell | Phillipe Flatresse | 2004-08-17 |