Issued Patents All Time
Showing 226–250 of 283 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9396984 | Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region | Maud Vinet, Romain Wacquez | 2016-07-19 |
| 9385051 | Method for the formation of a FinFET device having partially dielectric isolated fin structure | Ronald K. Sampson | 2016-07-05 |
| 9368411 | Method for the formation of fin structures for FinFET devices | Qing Liu | 2016-06-14 |
| 9349730 | Fin transformation process and isolation structures facilitating different Fin isolation schemes | Ajey Poovannummoottil Jacob, Kangguo Cheng, Bruce B. Doris, Prasanna Khare, Ramachandra Divakaruni | 2016-05-24 |
| 9337079 | Prevention of contact to substrate shorts | Qing Liu, Shom Ponoth | 2016-05-10 |
| 9263580 | Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device | Ajey Poovannummoottil Jacob | 2016-02-16 |
| 9263343 | Dual EPI CMOS integration for planar substrates | Balasubramanian Pranatharthiharan | 2016-02-16 |
| 9257450 | Semiconductor device including groups of stacked nanowires and related methods | James Kuss | 2016-02-09 |
| 9252052 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Maud Vinet | 2016-02-02 |
| 9245953 | Method to induce strain in 3-D microfabricated structures | Pierre Morin | 2016-01-26 |
| 9236380 | Semiconductor-on-insulator (SOI) device and related methods for making same using non-oxidizing thermal treatment | Pierre Morin, Qing Liu | 2016-01-12 |
| 9230991 | Method to co-integrate oppositely strained semiconductor devices on a same substrate | Sylvain Maitrejean, Romain Wacquez | 2016-01-05 |
| 9219078 | Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Scott Luning | 2015-12-22 |
| 9219133 | Method of making a semiconductor device using spacers for source/drain confinement | Pierre Morin | 2015-12-22 |
| 9190517 | Methods for making a semiconductor device with shaped source and drain recesses and related devices | Douglas Charles LaTulipe, Alexander Reznicek | 2015-11-17 |
| 9171757 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Maud Vinet | 2015-10-27 |
| 9166049 | Method to enhance strain in fully isolated finFET structures | Ali Khakifirooz, Pierre Morin, Sanjay C. Mehta | 2015-10-20 |
| 9166023 | Bulk finFET semiconductor-on-nothing integration | Prasanna Khare, Jin Cho | 2015-10-20 |
| 9136384 | Method for the formation of a FinFET device having partially dielectric isolated Fin structure | Ronald K. Sampson | 2015-09-15 |
| 9123809 | Transistor having a stressed body | Prasanna Khare, Qing Liu | 2015-09-01 |
| 9105663 | FinFET with silicon germanium stressor and method of forming | Kangguo Cheng, Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek, Raghavasimhan Sreenivasan +1 more | 2015-08-11 |
| 9099570 | Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices | Prasanna Khare | 2015-08-04 |
| 9099565 | Method of making a semiconductor device using trench isolation regions to maintain channel stress | Qing Liu | 2015-08-04 |
| 9099559 | Method to induce strain in finFET channels from an adjacent region | Pierre Morin | 2015-08-04 |
| 9093556 | Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods | Qing Liu, Prasanna Khare | 2015-07-28 |