Issued Patents All Time
Showing 176–200 of 283 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9917194 | Self-aligned silicon germanium FinFET with relaxed channel region | Pierre Morin | 2018-03-13 |
| 9911656 | Wimpy device by selective laser annealing | Kangguo Cheng, Xin Miao, Alexander Reznicek | 2018-03-06 |
| 9905662 | Method of making a semiconductor device using a dummy gate | Prasanna Khare | 2018-02-27 |
| 9905478 | Co-integration of tensile silicon and compressive silicon germanium | Pierre Morin, Yann Mignot | 2018-02-27 |
| 9893147 | Fully substrate-isolated FinFET transistor | Prasanna Khare | 2018-02-13 |
| 9882006 | Silicon germanium fin channel formation | Hong He, Junli Wang | 2018-01-30 |
| 9865587 | Method and structure for forming buried ESD with FinFETs | Kangguo Cheng, Xin Miao, Alexander Reznicek | 2018-01-09 |
| 9859426 | Semiconductor device including optimized elastic strain buffer | Yann Mignot, Pierre Morin | 2018-01-02 |
| 9847260 | Method to co-integrate SiGe and Si channels for finFET devices | Prasanna Khare, Qing Liu | 2017-12-19 |
| 9842929 | Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate | Kangguo Cheng, Xin Miao, Alexander Reznicek | 2017-12-12 |
| 9831342 | Method to induce strain in 3-D microfabricated structures | Pierre Morin | 2017-11-28 |
| 9806196 | Semiconductor device with fin and related methods | Pierre Morin | 2017-10-31 |
| 9793378 | Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability | Shom Ponoth, Prasanna Khare, Qing Liu, Balasubramanian Pranatharthiharan | 2017-10-17 |
| 9768055 | Isolation regions for SOI devices | Qing Liu, Prasanna Khare, Shom Ponoth, Maud Vinet, Bruce B. Doris | 2017-09-19 |
| 9761699 | Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures | Bruce B. Doris, Hong He, Junli Wang | 2017-09-12 |
| 9761722 | Isolation of bulk FET devices with embedded stressors | Hemanth Jagannathan | 2017-09-12 |
| 9755017 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Michael A. Guillorn, Isaac Lauer | 2017-09-05 |
| 9741626 | Vertical transistor with uniform bottom spacer formed by selective oxidation | Kangguo Cheng, Xin Miao, Alexander Reznicek | 2017-08-22 |
| 9735062 | Defect reduction in channel silicon germanium on patterned silicon | Bruce B. Doris, Alexander Reznicek, Joshua M. Rubin | 2017-08-15 |
| 9716158 | Air gap spacer between contact and gate region | Kangguo Cheng, Xin Miao, Alexander Reznicek | 2017-07-25 |
| 9716086 | Method and structure for forming buried ESD with FinFETs | Kangguo Cheng, Xin Miao, Alexander Reznicek | 2017-07-25 |
| 9716173 | Compressive strain semiconductor substrates | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9685380 | Method to co-integrate SiGe and Si channels for finFET devices | Prasanna Khare, Qing Liu | 2017-06-20 |
| 9685555 | High-reliability, low-resistance contacts for nanoscale transistors | Qing Liu, Chun-Chen Yeh, Ruilong Xie, Xiuyu Cai | 2017-06-20 |
| 9679899 | Co-integration of tensile silicon and compressive silicon germanium | Pierre Morin, Yann Mignot | 2017-06-13 |