Issued Patents All Time
Showing 426–450 of 471 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5521399 | Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit | Shao-fu Sanford Chu, Chang-Ming Hsieh, Kyong-Min Kim, Shaw-Ning Mei | 1996-05-28 |
| 5516721 | Isolation structure using liquid phase oxide deposition | Carol Galli, Seiki Ogura, Joseph F. Shepard, Jr. | 1996-05-14 |
| 5484738 | Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits | Shao-fu Sanford Chu, Chang-Ming Hsieh, Kyong-Min Kim, Shaw-Ning Mei | 1996-01-16 |
| 5470781 | Method to reduce stress from trench structure on SOI wafer | Dureseti Chidambarrao, J. Daniel Mis, James Peng | 1995-11-28 |
| 5470681 | Phase shift mask using liquid phase oxide deposition | Timothy A. Brunner, Derek B. Dove | 1995-11-28 |
| 5465859 | Dual phase and hybrid phase shifting mask fabrication using a surface etch monitoring technique | Jonathan D. Chapple-Sokol, Paul J. Tsang, Chi-Min Yuan | 1995-11-14 |
| 5466625 | Method of making a high-density DRAM structure on SOI | Chang-Ming Hsieh, Seiki Ogura | 1995-11-14 |
| 5446312 | Vertical-gate CMOS compatible lateral bipolar transistor | Chang-Ming Hsieh, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr. | 1995-08-29 |
| 5426330 | Refractory metal capped low resistivity metal conductor lines and vias | Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal | 1995-06-20 |
| 5405795 | Method of forming a SOI transistor having a self-aligned body contact | Klaus D. Beyer, Taqi Nasser Buti, Chang-Ming Hsieh | 1995-04-11 |
| 5403779 | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD | Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal | 1995-04-04 |
| 5395786 | Method of making a DRAM cell with trench capacitor | Sieki Ogura, Joseph F. Shepard, Jr. | 1995-03-07 |
| 5391510 | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps | Gangadhara S. Mathad, Rajiv V. Joshi | 1995-02-21 |
| 5389559 | Method of forming integrated interconnect for very high density DRAMs | Chang-Ming Hsieh, Toshio Mii, Seiki Ogura, Joseph F. Shepard, Jr. | 1995-02-14 |
| 5384152 | Method for forming capacitors with roughened single crystal plates | Jack C. Chu, Toshio Mii, Joseph F. Shepard, Jr., Scott R. Stiffler, Manu J. Tejwani +1 more | 1995-01-24 |
| 5384277 | Method for forming a DRAM trench cell capacitor having a strap connection | Toshio Mii, Joseph F. Shepard, Jr., Seiki Ogura | 1995-01-24 |
| 5382832 | Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding | Taqi Nasser Buti, Rajiv V. Joshi, Joseph F. Shepard, Jr. | 1995-01-17 |
| 5376578 | Method of fabricating a semiconductor device with raised diffusions and isolation | Seiki Ogura, Joseph F. Shepard, Jr. | 1994-12-27 |
| 5371022 | Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor | Chang-Ming Hsieh, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr. | 1994-12-06 |
| 5369049 | DRAM cell having raised source, drain and isolation | Joyce Elizabeth Acocella, Seiki Ogura, Nivo Rovedo, Joseph F. Shepard, Jr. | 1994-11-29 |
| 5366923 | Bonded wafer structure having a buried insulation layer | Klaus D. Beyer, Chang-Ming Hsieh, Tsorng-Dih Yuan | 1994-11-22 |
| 5340759 | Method of making a vertical gate transistor with low temperature epitaxial channel | Chang-Ming Hsieh, Seiki Ogura | 1994-08-23 |
| 5341023 | Novel vertical-gate CMOS compatible lateral bipolar transistor | Chang-Ming Hsieh, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr. | 1994-08-23 |
| 5315151 | Transistor structure utilizing a deposited epitaxial base region | Chang-Ming Hsieh, Victor J. Silvestri | 1994-05-24 |
| 5313094 | Thermal dissipation of integrated circuits using diamond paths | Klaus D. Beyer, Chang-Ming Hsieh, David E. Kotecki, Tsoring-Dih Yuan | 1994-05-17 |