Issued Patents All Time
Showing 401–425 of 471 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5874764 | Modular MOSFETS for high aspect ratio applications | Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-fu Sanford Chu | 1999-02-23 |
| 5872733 | Ramp-up rate control circuit for flash memory charge pump | Taqi Nasser Buti, Jente B. Kuang, Somnuk Ratanaphanyarat, Mary J. Saccamango, Hyun Jong Shin | 1999-02-16 |
| 5811857 | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications | Fariborz Assaderaghi, Jack A. Mandelman, Ghavam G. Shahidi, Steven H. Voldman | 1998-09-22 |
| 5784311 | Two-device memory cell on SOI for merged logic and memory applications | Fariborz Assaderaghi, Bijan Davari, Jack A. Mandelman, Ghavam G. Shahidi | 1998-07-21 |
| 5780327 | Vertical double-gate field effect transistor | Jack O. Chu, Jack A. Mandelman, Yuan-Chen Sun, Yuan Taur | 1998-07-14 |
| 5774411 | Methods to enhance SOI SRAM cell stability | Chang-Ming Hsieh, Jack A. Mandelman, Mario M. Pelella | 1998-06-30 |
| 5770875 | Large value capacitor for SOI | Fariborz Assaderaghi, Jack A. Mandelman, William R. Tonti | 1998-06-23 |
| 5759907 | Method of making large value capacitor for SOI | Fariborz Assaderaghi, Jack A. Mandelman, William R. Tonti | 1998-06-02 |
| 5753525 | Method of making EEPROM cell with improved coupling ratio | Seiki Ogura, James Peng | 1998-05-19 |
| 5736891 | Discharge circuit in a semiconductor memory | Taqi Nasser Buti, Jente B. Kuang, Somnuk Ratanaphanyarat, Mary J. Saccamango, Hyun Jong Shin | 1998-04-07 |
| 5729039 | SOI transistor having a self-aligned body contact | Klaus D. Beyer, Taqi Nasser Buti, Chang-Ming Hsieh | 1998-03-17 |
| 5721144 | Method of making trimmable modular MOSFETs for high aspect ratio applications | Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-fu Sanford Chu | 1998-02-24 |
| 5721485 | High performance on-chip voltage regulator designs | Toshiaki Kirihata, Somnuk Ratanaphanyarat, Hyun Jong Shin | 1998-02-24 |
| 5689127 | Vertical double-gate field effect transistor | Jack O. Chu, Jack A. Mandelman, Yuan-Chen Sun, Yuan Taur | 1997-11-18 |
| 5675164 | High performance multi-mesa field effect transistor | Timothy A. Brunner, Jack A. Mandelman, Li-Kong Wang | 1997-10-07 |
| 5663578 | Thin film transistor with self-aligned bottom gate | Mary J. Saccamango, Joseph F. Shepard, Jr. | 1997-09-02 |
| 5643813 | Packing density for flash memories by using a pad oxide | Joyce Elizabeth Acocella, Carol Galli, Seiki Ogura, Nivo Rovedo, Joseph F. Shepard, Jr. | 1997-07-01 |
| 5633522 | CMOS transistor with two-layer inverse-T tungsten gate | Fernand Dorleans, Liang-Choo Hsia, Gerald R. Larsen, Geraldine C. Schwartz | 1997-05-27 |
| 5622881 | Packing density for flash memories | Joyce Elizabeth Acocella, Carol Galli, Seiki Ogura, Nivo Rovedo, Joseph F. Shepard, Jr. | 1997-04-22 |
| 5599725 | Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure | Fernand Dorleans, Liang-Choo Hsia, Gerald R. Larsen, Geraldine C. Schwartz | 1997-02-04 |
| 5585673 | Refractory metal capped low resistivity metal conductor lines and vias | Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal | 1996-12-17 |
| 5573964 | Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer | Mary J. Saccamango, Joseph F. Shepard, Jr. | 1996-11-12 |
| 5567553 | Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures | Chang-Ming Hsieh, Lyndon R. Logan | 1996-10-22 |
| 5532089 | Simplified fabrication methods for rim phase-shift masks | William J. Adair, Timothy A. Brunner, Derek B. Dove, Chi-Min Yuan | 1996-07-02 |
| 5528062 | High-density DRAM structure on soi | Chang-Ming Hsieh, Seiki Ogura | 1996-06-18 |