Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5633522 | CMOS transistor with two-layer inverse-T tungsten gate | Fernand Dorleans, Liang-Choo Hsia, Louis L. Hsu, Gerald R. Larsen | 1997-05-27 |
| 5599725 | Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure | Fernand Dorleans, Liang-Choo Hsia, Louis L. Hsu, Gerald R. Larsen | 1997-02-04 |
| 5340775 | Structure and fabrication of SiCr microfuses | Roy A. Carruthers, Fernand Dorleans, John A. Fitzsimmons, Richard Flitsch, James A. Jubinsky +3 more | 1994-08-23 |
| 5285099 | SiCr microfuses | Roy A. Carruthers, Fernand Dorleans, John A. Fitzsimmons, Richard Flitsch, James A. Jubinsky +3 more | 1994-02-08 |
| 4675072 | Trench etch endpoint detection by LIF | Reid S. Bennett, Linda M. Ephrath, Gary S. Selwyn | 1987-06-23 |
| 4601939 | Composite insulator structure | George Gati, Albert P. Lee, Charles L. Standley | 1986-07-22 |
| 4447824 | Planar multi-level metal process with built-in etch stop | Joseph S. Logan, John L. Mauer, IV, Laura Rothman, Charles L. Standley | 1984-05-08 |
| 4396458 | Method for forming planar metal/insulator structures | Valeria Platter, Laura Rothman, Paul M. Schaible | 1983-08-02 |
| 4368220 | Passivation of RIE patterned al-based alloy films by etching to remove contaminants and surface oxide followed by oxidation | Jerome M. Eldridge, Michael H. Lee | 1983-01-11 |
| 4367119 | Planar multi-level metal process with built-in etch stop | Joseph S. Logan, John L. Mauer, IV, Laura Rothman, Charles L. Standley | 1983-01-04 |
| 4352716 | Dry etching of copper patterns | Paul M. Schaible | 1982-10-05 |
| 4183781 | Stabilization process for aluminum microcircuits which have been reactive-ion etched | Jerome M. Eldridge, Wen-Yaung Lee | 1980-01-15 |